【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch06
摘要：
Chapter 6. Dataflow Modeling6.7 Exercises1. A full subtractor has three 1-bit inputs x,y,and z(previous borrow) and two 1-bit outputs D(difference) and B(borrow). The logic equations for D and B are as follows: D=x’.y’.z + x’.y.z’ + x.y’.z’ + x.y.z B=x’.y + x’.z + y.z Write the full Verilog descript 阅读全文
posted @ 2011-03-15 20:07 yf.x 阅读(13278) 评论(1) 推荐(0) 编辑
