【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05
摘要：
Chapter 5. Gate-level Modeling5.4 Exercises1. Create your own 2-input Verilog gates called my_or, my_and and my_not from 2-input nand gates. Check the functionality of these gates with a stimulus module. my answer: 2. A 2-input xor gate can be built from my_and, my_or and my_not gates. Construct an 阅读全文
posted @ 2011-03-13 18:45 yf.x 阅读(20544) 评论(0) 推荐(0) 编辑
