【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch04
摘要：
Chapter 4. Modules and Ports4.5 Exercises1. What are the basic components of a module? Which components are mandatory? my answer: 1) Module Name, Port List, Port Declarations, Parameters, Declarations of wires, regs and other variables, Data flow statements, Instantiation of lower level modules, alw 阅读全文
posted @ 2011-03-12 13:21 yf.x 阅读(7965) 评论(0) 推荐(0) 编辑
