[笔记]再笔记--边干边学Verilog HDL --001

缘起

   

    偶然，借到块DE2，开始学习Verilog HDL，也是从语法看起，照着书上敲代码，仿真，做lab，下载，貌似入门了，但总是不确定，总是觉得不能把握什么。偶然看到akuei2的《Verilog哪些事儿--建模篇》V4，觉得很好，遂想记录“打谱”的点滴--是为再笔记。

Lab 1 永远的流水灯

    这名字是直接拿来的，起的太好了，不多言。

   

    这个实验想阐述并行的思想，用4个类似的模块建立1个并行操作的流水灯模块。每隔100ms流动一下。

代码：

led0_module.v

/**
 * File name: led0_mocule.v
 *
 */
 
 module led0_module
(
    clk, rst_n, led_out
);

    input clk;
    input rst_n;
    output led_out;
    
    parameter T10MS = 25'd20_000_000;
     
    reg [24:0] count;
    
    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            count <= 25'd0;
         else if (count == T10MS)
            count <= 25'd0;
         else
            count <= count + 1'b1;
             
    reg rled_out;

    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            rled_out <= 1'b0;
         else if (count >= 25'd0 && count < 25'd5_000_000)
            rled_out <= 1'b1;
         else
            rled_out <= 1'b0;
            
    assign led_out = rled_out;

endmodule    
    

led1_module.v

/**
 * File name: led1_mocule.v
 *
 */
 
module led1_module
(
    clk, rst_n, led_out
);

    input clk;
    input rst_n;
    output led_out;
    
    parameter T10MS = 25'd20_000_000;
    
    reg [24:0] count;
    
    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            count <= 25'd0;
        else if (count == T10MS)
            count <= 25'd0;
        else
            count <= count + 1'b1;
            
    reg rled_out;

    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            rled_out <= 1'b0;
        else if (count >= 25'd5_000_000 && count < 25'd10_000_000)
            rled_out <= 1'b1;
        else
            rled_out <= 1'b0;
            
    assign led_out = rled_out;

endmodule    
    

led2_module.v

/**
 * File name: led2_mocule.v
 *
 */
 
module led2_module
(
    clk, rst_n, led_out
);

    input clk;
    input rst_n;
    output led_out;
    
    parameter T10MS = 25'd20_000_000;
    
    reg [24:0] count;
    
    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            count <= 25'd0;
        else if (count == T10MS)
            count <= 25'd0;
        else
            count <= count + 1'b1;
            
    reg rled_out;

    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            rled_out <= 1'b0;
        else if (count >= 25'd10_000_000 && count < 25'd15_000_000)
            rled_out <= 1'b1;
        else
            rled_out <= 1'b0;
            
    assign led_out = rled_out;

endmodule    
    

led3_module.v

/**
 * File name: led3_mocule.v
 *
 */
 
module led3_module
(
    clk, rst_n, led_out
);

    input clk;
    input rst_n;
    output led_out;
    
    parameter T10MS = 25'd20_000_000;
    
    reg [24:0] count;
    
    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            count <= 25'd0;
        else if (count == T10MS)
            count <= 25'd0;
        else
            count <= count + 1'b1;
            
    reg rled_out;

    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            rled_out <= 1'b0;
        else if (count >= 25'd15_000_000 && count < 25'd20_000_000)
            rled_out <= 1'b1;
        else
            rled_out <= 1'b0;
            
    assign led_out = rled_out;

endmodule    
    

top_module.v

/**
 * File name: top_module.v
 * Function: moving lamp, time interval = 0.1s.
 * Pins: KEY0-rst_n, LEDG3-0
 * Target board: DE2.
 * Software: Quartus II 9.1 sp1  
 * ----------------------------
 * yf.x
 * 7-11-2011
 *        
 */
 
module top_module
(
    CLOCK_50, KEY, LEDG
);

    input CLOCK_50;
    input [0:0] KEY;
    output [3:0] LEDG;
    
    wire led0_out;
    
    led0_module U0
    (
        .clk (CLOCK_50),
        .rst_n (KEY[0]),
        .led_out (led0_out)
    );

    wire led1_out;
    
    led1_module U1
    (
        .clk (CLOCK_50),
        .rst_n (KEY[0]),
        .led_out (led1_out)
    );
    
    wire led2_out;
    
    led2_module U2
    (
        .clk (CLOCK_50),
        .rst_n (KEY[0]),
        .led_out (led2_out)
    );
    
    wire led3_out;
    
    led3_module U3
    (
        .clk (CLOCK_50),
        .rst_n (KEY[0]),
        .led_out (led3_out)
    );
    
    assign LEDG[3:0] = {led3_out, led2_out, led1_out, led0_out};
    
endmodule    

RTL图

小结

    并行思维.