【笔记】Verilog HDL 关键词【Verilog HDL】

Verilog HDL 关键词
always	and	assign	automatic
begin	buf	bufif0	bufif1
case	casex	casez	cell
cmos	config
deassign disable	default	defparam	design
endconfig	endfunction	endgenerate	endmodule
endprimitive event	endspecify	endtable	endtask
for	force	forever	fork
function
generate	genvar
highz0	highz1
if	ifnone	incdir	include
initial	inout	input	instance
integer
join
large	liblist	library	localparam
macromdule	medium	module
nand	negedge	nmos	nor

noshowcancelled	not	notif0
notif1
or	output
parameter	pmos	posedge	primitive
pull0	pull1	pulldown	pullup
pulsestyle_onevent	pusestyle_ondetect
rcmos	real	realtime	reg
release	repeat	rnmos	rpmos
rtran	rtranif0	rtranif1
scalared	showcancelled	signed	small
specify	specparam	strong0	strong1
supply0	supply1
table	task	time	tran
tranif0	tranif1	tri	tri0
tri1	triand	trior	trireg
unsigned	use
vectored
wait	wand	weak0	weak1
while	wire	wor
xnor	xor

 

注：整理自《Verilog HDL 入门》（3rd）