摘要：
《数字系统设计与Verilog HDL》上面有这么一段代码，用于实现8位4级流水线加法器。module adder8pip(cout,sum,cin,ina,inb,clk );input cin,clk;input [7:0] ina,inb;output cout;output [7:0] sum;reg cout,tempcin;reg [7:0] sum,tempa,tempb;reg firstco,secondco,thirdco; //前三级加法的进位输出reg [1:0] firstsum,thirdina,thirdinb;reg [3:0] secondsum,sec... 阅读全文
