在Quartus16.1下使用ModelSim对vhdl写的项目进行仿真

首先新建一个工程并编写VHDL文件

我编写的是decoder3_8

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

entity decoder3_8 is
port(
a,b,c,en:in std_logic;
y:out std_logic_vector(7 downto 0));
end decoder3_8;

architecture rtl of decoder3_8 is
signal data:std_logic_vector(2 downto 0);
begin
data<=c&b&a;
process(data,en)
begin
    if(en='1') then
        case data is
            when "000"=>y<="11111110";
            when "001"=>y<="11111101";
            when "010"=>y<="11111011";
            when "011"=>y<="11110111";
            when "100"=>y<="11101111";
            when "101"=>y<="11011111";
            when "110"=>y<="10111111";
            when "111"=>y<="01111111";
            when others=>y<="11111111";
        end case;
    else
        y<="11111111";
    end if;
end process;
end rtl;