hdlbits之Exams/ece241 2013 q4的FSM问题

工作和学习中的事情太多，想干的事情更多，所以总感觉时间不够用。再加上自己比较懒，好久没有兴致闲下来写东西了。

之前做过hdlbits的一些题目，挺简单。但是今天被这道题给坑惨了，花费了几个小时才做出来。不是说这道题有多难，一是自己犯了一个脑袋驴踢的及其低级错误，二是题目也有出的不清楚的地方。原题目如下

 

自己犯下的极其低级和愚蠢的错误为在S0,S1,S2,S3四个状态，判断输入s的值是忘了加数据类型和位宽。这个愚蠢而又低级的错误导致无法进入正确的状态。

            S0 : begin
                case(s)
                    000 : next_state = S0;
                    001 : next_state = S1;
                    011 : next_state = S2;
                    111 : next_state = S3;
                    default: next_state = S0;
                endcase                
            end

正确的应该如下所示：

            S0 : begin
                case(s)
                    3'b000 : next_state = S0;
                    3'b001 : next_state = S1;
                    3'b011 : next_state = S2;
                    3'b111 : next_state = S3;
                    default: next_state = S0;
                endcase                
            end

第二个原题目中没有交代清楚的问题：题目中之说了如果之前水位低于当前水位，为正常水流（即dfr不用打开），如果之前水位大于当前水位，则需要打开dfr。没有说当之前水位与当前水位相同时怎么处理dfr。导致自己这个地方一直出错，最后观察作者的测试波形，才发现作者的愿意是这种情况dfr保持之前的值。这个地方挺坑爹的。

最后代码如下：

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 

    parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
    reg       [1:0] current_state, next_state, last_state;

    always @(posedge clk) begin
        if(reset) begin
            current_state <= S0;
            last_state    <= S0;
        end
        else begin
            current_state <= next_state;
            last_state    <= current_state;
        end
    end
    
    always @(*) begin
        case(current_state)
            S0 : begin
                case(s)
                    3'b000 : next_state = S0;
                    3'b001 : next_state = S1;
                    3'b011 : next_state = S2;
                    3'b111 : next_state = S3;
                    default: next_state = S0;
                endcase                
            end
            S1 : begin
                case(s)
                    3'b000 : next_state = S0;
                    3'b001 : next_state = S1;
                    3'b011 : next_state = S2;
                    3'b111 : next_state = S3;
                    default: next_state = S0;
                endcase                
            end
            S2 : begin
                case(s)
                    3'b000 : next_state = S0;
                    3'b001 : next_state = S1;
                    3'b011 : next_state = S2;
                    3'b111 : next_state = S3;
                    default: next_state = S0;
                endcase                
            end
            S3 : begin
                case(s)
                    3'b000 : next_state = S0;
                    3'b001 : next_state = S1;
                    3'b011 : next_state = S2;
                    3'b111 : next_state = S3;
                    default: next_state = S0;
                endcase                
            end
            default: next_state = S0;
        endcase       
    end
    
    always @(*) begin
        case(current_state)
            S0 : {fr3,fr2,fr1} = 3'b111;
            S1 : {fr3,fr2,fr1} = 3'b011;
            S2 : {fr3,fr2,fr1} = 3'b001;
            S3 : {fr3,fr2,fr1} = 3'b000;
            default: {fr3,fr2,fr1} = 3'b111;
        endcase
    end
    //assign fr3 = (current_state == S0);
    //assign fr2 = (current_state == S0) || (current_state == S1);
    //assign fr1 = (current_state == S0) || (current_state == S1) || (current_state == S2);
    
    always @(*) begin
        if(current_state == S0)
            dfr = 1'b1;
        else if(last_state > current_state)
            dfr = 1'b1;
        else if(last_state < current_state)
            dfr = 1'b0;
        else
            dfr = dfr;   //will generate latch        
    end
    
endmodule

 原作者的非常简洁。主要区别在于自己的写法是以水位的状态为状态机的各种状态。这个状态机相对简单，但是dfr的情况无法在状态机中体现（即没有考虑水位从高到底的情况下dfr的值）。原作者通过细分状态的方式，简化了dfr的verilog代码逻辑。非常漂亮。原作者代码如下：

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);


    // Give state names and assignments. I'm lazy, so I like to use decimal numbers.
    // It doesn't really matter what assignment is used, as long as they're unique.
    // We have 6 states here.
    parameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;
    reg [2:0] state, next;        // Make sure these are big enough to hold the state encodings.
    


    // Edge-triggered always block (DFFs) for state flip-flops. Synchronous reset.    
    always @(posedge clk) begin
        if (reset) state <= A2;
        else state <= next;
    end



    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.    
    always@(*) begin
        case (state)
            A2: next = s[1] ? B1 : A2;
            B1: next = s[2] ? C1 : (s[1] ? B1 : A2);
            B2: next = s[2] ? C1 : (s[1] ? B2 : A2);
            C1: next = s[3] ? D1 : (s[2] ? C1 : B2);
            C2: next = s[3] ? D1 : (s[2] ? C2 : B2);
            D1: next = s[3] ? D1 : C2;
            default: next = 'x;
        endcase
    end
    
    
    
    // Combinational output logic. In this problem, a procedural block (combinational always block) 
    // is more convenient. Be careful not to create a latch.
    always@(*) begin
        case (state)
            A2: {fr3, fr2, fr1, dfr} = 4'b1111;
            B1: {fr3, fr2, fr1, dfr} = 4'b0110;
            B2: {fr3, fr2, fr1, dfr} = 4'b0111;
            C1: {fr3, fr2, fr1, dfr} = 4'b0010;
            C2: {fr3, fr2, fr1, dfr} = 4'b0011;
            D1: {fr3, fr2, fr1, dfr} = 4'b0000;
            default: {fr3, fr2, fr1, dfr} = 'x;
        endcase
    end
    
endmodule

 状态图的s1s2s3排列方式不好，如果改为S3S2S1会更符合习惯。