modelsim仿真第一步

参考网址：https://blog.csdn.net/weixin_43506155/article/details/118179930?spm=1001.2101.3001.6661.1&utm_medium=distribute.pc_relevant_t0.none-task-blog-2~default~CTRLIST~Rate-1.pc_relevant_default&depth_1-utm_source=distribute.pc_relevant_t0.none-task-blog-2~default~CTRLIST~Rate-1.pc_relevant_default&utm_relevant_index=1

代码：

module led0_module(CLK, RSTn, LED_out);
    input CLK;
    input RSTn;
    output LED_out;
    
    /********************************/
    parameter T1S = 26'd50;
    /********************************/
    
    reg [25:0] Count1;
    
    always @(posedge CLK or negedge RSTn)
        if(!RSTn)
            Count1 <= 26'd0;
        else if(Count1 == T1S)
            Count1 <= 26'd0;
        else
            Count1 <= Count1 + 1'b1;
            
    /********************************/
    
    reg rLED_out;
    always @(posedge CLK or negedge RSTn)
        if(!RSTn)
            rLED_out <= 1'b0;
        else if(Count1 >= 26'd0 && Count1 < 26'd25)
            rLED_out <= 1'b1;
        else
            rLED_out <= 1'b0;
            
    /********************************/
    
    assign LED_out = rLED_out;
    
    /********************************/
    
endmodule

led0_tb.vb

`timescale 1 ns/ 1 ns//仿真的单位时间为1ns， 精度为1ps
module led0_tb;
    reg clk;
    reg rstn;
    wire led0_out;
    initial
    begin
        rstn = 0;
        #10 rstn = 1;
        clk = 0;
        frever #1 clk = ~clk;
    end
    
led0_module U1(
    .CLK(clk), 
    .RSTn(rstn), 
    .LED_out(led0_out)
);

endmodule

 

module decode38(data_in,data_out,enable);
  input [2:0] data_in;  //???????38????8?????
  output [7:0] data_out;  //???????38????3?????
  input enable; //????????????
  reg [7:0] data_out; //????????????????????always??????
  always @(data_in or enable) begin //???????????????????always?????
    if (enable==1)  //??????????????
      case (data_in)
        3'b000: data_out=8'b11111110;
        3'b001: data_out=8'b11111101;
        3'b010: data_out=8'b11111011;
        3'b011: data_out=8'b11110111;
        3'b100: data_out=8'b11101111;
        3'b101: data_out=8'b11011111;
        3'b110: data_out=8'b10111111;
        3'b111: data_out=8'b01111111;
        default: data_out=8'bxxxxxxxx;
      endcase
    else  //????????
      data_out=8'b11111111;
  end
endmodule

module decode38_tb;  //???????????????????????????????????????
  reg [2:0]data_in_tb;  //???????????
  wire [7:0]data_out_tb;  //??????????
  reg enable_tb;  //???????????????
  decode38 t1(data_in_tb,data_out_tb,enable_tb);  //???????????????????????????????????????????
  initial begin
    enable_tb=0;
    data_in_tb=0;
    #20 enable_tb=1;  //??20???????????????50??????????????????????????????
    #50 data_in_tb=0;
    #50 data_in_tb=1;
    #50 data_in_tb=2;
    #50 data_in_tb=3;
    #50 data_in_tb=4;
    #50 data_in_tb=5;
    #50 data_in_tb=6;
    #50 data_in_tb=7;
    #50 $finish();
  end
endmodule