基于devkit8600的2011.04版uboot启动代码Start.s分析
/* * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core * * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> * * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> * Copyright (c) 2003 Kshitij <kshitij@ti.com> * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <asm-offsets.h> #include <config.h> #include <version.h> .globl _start _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq #ifdef CONFIG_SPL_BUILD _undefined_instruction: .word _undefined_instruction _software_interrupt: .word _software_interrupt _prefetch_abort: .word _prefetch_abort _data_abort: .word _data_abort _not_used: .word _not_used _irq: .word _irq _fiq: .word _fiq _pad: .word 0x12345678 /* now 16*4=64 */ #else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_SPL_BUILD */ .global _end_vect _end_vect: .balignl 16,0xdeadbeef /************************************************************************* * * Startup Code (reset vector) * * do important init only if we don't start from memory! * setup Memory and board specific bits prior to relocation. * relocate armboot to ram * setup stack * *************************************************************************/ .globl _TEXT_BASE _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE #ifdef CONFIG_TEGRA2 /* * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU * to pick up its reset vector, which points here. */ .globl _armboot_start _armboot_start: .word _start #endif /* * These are defined in the board-specific linker script. */ .globl _bss_start_ofs _bss_start_ofs: .word __bss_start - _start .global _image_copy_end_ofs _image_copy_end_ofs: .word __image_copy_end - _start .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start .globl _end_ofs _end_ofs: .word _end - _start #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START IRQ_STACK_START: .word 0x0badc0de /* IRQ stack memory (calculated at run-time) */ .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de #endif /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: .word 0x0badc0de /* * the actual reset code */ reset: bl save_boot_params
/**************************************************************************/
save_boot_params
在arch/arm/cpu/armv7/cpu.c中定义
在arch/arm/cpu/armv7/ti81xx/lowlevel_init.s中生重定义
/**************************************************************************/
/* * set the cpu to SVC32 mode */ mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0xd3 msr cpsr,r0 #if defined(CONFIG_OMAP34XX) /* Copy vectors to mask ROM indirect addr */ adr r0, _start @ r0 <- current position of code add r0, r0, #4 @ skip reset vector mov r2, #64 @ r2 <- size to copy add r2, r0, r2 @ r2 <- source end address mov r1, #SRAM_OFFSET0 @ build vect addr mov r3, #SRAM_OFFSET1 add r1, r1, r3 mov r3, #SRAM_OFFSET2 add r1, r1, r3 next: ldmia r0!, {r3 - r10} @ copy from source address [r0] stmia r1!, {r3 - r10} @ copy to target address [r1] cmp r0, r2 @ until source end address [r2] bne next @ loop until equal */ #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) /* No need to copy/exec the clock code - DPLL adjust already done * in NAND/oneNAND Boot. */ bl cpy_clk_code @ put dpll adjust code behind vectors #endif /* NAND Boot */ #endif /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit
/**************************************************************************/
cpu_init_crit在本文件中定义
/**************************************************************************/
#endif /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r0,=0x00000000 bl board_init_f /*------------------------------------------------------------------------------*/
/**************************************************************************/
board_init_f在arch/arm/lib/board.c中定义,
/**************************************************************************/
/* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * */ .globl relocate_code relocate_code:
/**************************************************************************/
relocate_code由board_init_f返回,它的作用是初始化栈、清零bss段,之后跳到board_init_r,
并将
给gd指针和u-boot代码段地址()作为参数传进去
/**************************************************************************/
mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ /* Set up the stack */ stack_setup: mov sp, r4 adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r1!, {r9-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop #ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ fixloop: ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ add r0, r0, r9 /* r0 <- location to fix up in RAM */ ldr r1, [r2, #4] and r7, r1, #0xff cmp r7, #23 /* relative fixup? */ beq fixrel cmp r7, #2 /* absolute fixup? */ beq fixabs /* ignore unknown type of fixup */ b fixnext fixabs: /* absolute fix: set location to (offset) symbol value */ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ ldr r1, [r0] add r1, r1, r9 fixnext: str r1, [r0] add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop b clear_bss _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start #endif /* #ifndef CONFIG_SPL_BUILD */ clear_bss: #ifdef CONFIG_SPL_BUILD /* No relocation for SPL */ ldr r0, =__bss_start ldr r1, =__bss_end__ #else ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ add r0, r0, r4 add r1, r1, r4 #endif mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ jump_2_ram: /* * If I-cache is enabled invalidate it */ #ifndef CONFIG_SYS_ICACHE_OFF mcr p15, 0, r0, c7, c5, 0 @ invalidate icache mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 add lr, lr, r9 /* setup parameters for board_init_r */ mov r0, r5 /* gd_t */ mov r1, r6 /* dest_addr */ /* jump to it ... */ mov pc, lr
/**************************************************************************/
跳到board_init_r,它在arch/arm/lib/board.c中定义,其中:
LDR R0,Label 将程序标号地址连续的4个字节(1个字)的数据传送到目的寄存器中
ADR R0, _start把 _start地址读出来,而且这个地址是相对当前pc的,所以和当前程序运行地址相关,r0是代码的当前位置
ldr r0, _board_init_r_ofs //r0=board_init_r - _start(board_init_r偏移地址)
adr r1, _start //r1=_start的运行地址
add lr, r0, r1 //lr=board_init_r的真正运行地址
add lr, lr, r9 //r9保存重定向偏移大小,spl中 r9 = 0
mov r0, r5 //r0 = &gdata
mov r1, r6 //r6=CONFIG_SPL_TEXT_BASE
mov pc, lr //跳转到board_init_r
/**************************************************************************/
_board_init_r_ofs: .word board_init_r - _start #ifndef CONFIG_SKIP_LOWLEVEL_INIT /************************************************************************* * * CPU_init_critical registers * * setup important registers * setup memory timing * *************************************************************************/ cpu_init_crit: /* * Invalidate L1 I/D */ mov r0, #0 @ set up for MCR mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs mcr p15, 0, r0, c7, c5, 0 @ invalidate icache mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB /* * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB #ifdef CONFIG_SYS_ICACHE_OFF bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache #else orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache #endif mcr p15, 0, r0, c1, c0, 0 /* * Jump to board specific initialization... * The Mask ROM will have already initialized * basic memory. Go here to bump up clock rate and handle * wake up conditions. */ mov ip, lr @ persevere link reg across call bl lowlevel_init @ go setup pll,mux,memory
/**************************************************************************/
lowlevel_init在arch/arm/cpu/armv7/ti81xx/lowlevel_init.s中定义
/**************************************************************************/
mov lr, ip @ restore link mov pc, lr @ back to my caller #endif #ifndef CONFIG_SPL_BUILD /* ************************************************************************* * * Interrupt handling * ************************************************************************* */ @ @ IRQ stack frame. @ #define S_FRAME_SIZE 72 #define S_OLD_R0 68 #define S_PSR 64 #define S_PC 60 #define S_LR 56 #define S_SP 52 #define S_IP 48 #define S_FP 44 #define S_R10 40 #define S_R9 36 #define S_R8 32 #define S_R7 28 #define S_R6 24 #define S_R5 20 #define S_R4 16 #define S_R3 12 #define S_R2 8 #define S_R1 4 #define S_R0 0 #define MODE_SVC 0x13 #define I_BIT 0x80 /* * use bad_save_user_regs for abort/prefetch/undef/swi ... * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling */ .macro bad_save_user_regs sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current @ user stack stmia sp, {r0 - r12} @ Save user registers (now in @ svc mode) r0-r12 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort @ stack ldmia r2, {r2 - r3} @ get values for "aborted" pc @ and cpsr (into parm regs) add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack add r5, sp, #S_SP mov r1, lr stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr mov r0, sp @ save current stack into r0 @ (param register) .endm .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! @ a reserved stack spot would @ be good. stmdb r8, {sp, lr}^ @ Calling SP, LR str lr, [r8, #0] @ Save calling PC mrs r6, spsr str r6, [r8, #4] @ Save CPSR str r0, [r8, #8] @ Save OLD_R0 mov r0, sp .endm .macro irq_restore_user_regs ldmia sp, {r0 - lr}^ @ Calling r0 - lr mov r0, r0 ldr lr, [sp, #S_PC] @ Get PC add sp, sp, #S_FRAME_SIZE subs pc, lr, #4 @ return & move spsr_svc into @ cpsr .endm .macro get_bad_stack ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter @ in banked mode) str lr, [r13] @ save caller lr in position 0 @ of saved stack mrs lr, spsr @ get the spsr str lr, [r13, #4] @ save spsr in position 1 of @ saved stack mov r13, #MODE_SVC @ prepare SVC-Mode @ msr spsr_c, r13 msr spsr, r13 @ switch modes, make sure @ moves will execute mov lr, pc @ capture return pc movs pc, lr @ jump to next instruction & @ switch modes. .endm .macro get_bad_stack_swi sub r13, r13, #4 @ space on current stack for @ scratch reg. str r0, [r13] @ save R0's value. ldr r0, IRQ_STACK_START_IN @ get data regions start @ spots for abort stack str lr, [r0] @ save caller lr in position 0 @ of saved stack mrs r0, spsr @ get the spsr str lr, [r0, #4] @ save spsr in position 1 of @ saved stack ldr r0, [r13] @ restore r0 add r13, r13, #4 @ pop stack entry .endm .macro get_irq_stack @ setup IRQ stack ldr sp, IRQ_STACK_START .endm .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm /* * exception handlers */ .align 5 undefined_instruction: get_bad_stack bad_save_user_regs bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack_swi bad_save_user_regs bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs bl do_not_used #ifdef CONFIG_USE_IRQ .align 5 irq: get_irq_stack irq_save_user_regs bl do_irq irq_restore_user_regs .align 5 fiq: get_fiq_stack /* someone ought to write a more effective fiq_save_user_regs */ irq_save_user_regs bl do_fiq irq_restore_user_regs #else .align 5 irq: get_bad_stack bad_save_user_regs bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs bl do_fiq #endif /* CONFIG_USE_IRQ */ #endif /* CONFIG_SPL_BUILD */
/***************************************************************************** * lowlevel_init: - Platform low level init. * Corrupted Register : r0, r1, r2, r3, r4, r5, r6 ****************************************************************************/ .globl lowlevel_init lowlevel_init: /* The link register is saved in ip by start.S */ mov r6, ip /* check if we are already running from RAM */ ldr r2, _lowlevel_init ldr r3, _TEXT_BASE sub r4, r2, r3 sub r0, pc, r4 /* require dummy instr or subtract pc by 4 instead i'm doing stack init */ ldr sp, SRAM_STACK mark1: ldr r5, _mark1 sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */ sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */ mov r10, #0x0 /* r10 has in_ddr used by s_init() */ #ifdef CONFIG_NOR_BOOT cmp r0, #0x08000000 /* check for running from NOR */ beq ocmc_init_start /* if == then running from NOR */ ands r0, r0, #0xC0000000 /* MSB 2 bits <> 0 then we are in ocmc or DDR */ cmp r0, #0x40000000 /* if running from ocmc */ beq nor_init_start /* if == skip ocmc init and jump to nor init */ mov r10, #0x01 /* if <> we are running from DDR hence skip ddr init */ /* by setting in_ddr to 1 */ b s_init_start /* and jump to s_init */
/**************************************************************************/
s_init_start在本源代最后部分定义
/**************************************************************************/
#else ands r0, r0, #0xC0000000 /* MSB 2 bits <> 0 then we are in ocmc or DDR */ cmp r0, #0x80000000 bne s_init_start mov r10, #0x01 b s_init_start #endif #ifdef CONFIG_NOR_BOOT ocmc_init_start: /**** enable ocmc 0 ****/ /* CLKSTCTRL */ ldr r5, cm_alwon_ocmc_0_clkstctrl_addr mov r2, #0x2 str r2, [r5] /* wait for gpmc enable to settle */ ocmc0_wait0: ldr r2, [r5] #ifdef CONFIG_AM335X ands r2, r2, #0x00000100 cmp r2, #0x00000100 #else ands r2, r2, #0x00000010 cmp r2, #0x00000010 #endif bne ocmc0_wait0 /* CLKCTRL */ ldr r5, cm_alwon_ocmc_0_clkctrl_addr mov r2, #0x2 str r2, [r5] /* wait for gpmc enable to settle */ ocmc0_wait1: ldr r2, [r5] ands r2, r2, #0x00030000 cmp r2, #0 bne ocmc0_wait1 #ifndef CONFIG_AM335X /**** enable ocmc 1 ****/ /* CLKSTCTRL */ ldr r5, cm_alwon_ocmc_1_clkstctrl_addr mov r2, #0x2 str r2, [r5] /* wait for gpmc enable to settle */ ocmc1_wait0: ldr r2, [r5] ands r2, r2, #0x00000100 cmp r2, #0x00000100 bne ocmc1_wait0 /* CLKCTRL */ ldr r5, cm_alwon_ocmc_1_clkctrl_addr mov r2, #0x2 str r2, [r5] /* wait for gpmc enable to settle */ ocmc1_wait1: ldr r2, [r5] ands r2, r2, #0x00030000 cmp r2, #0 bne ocmc1_wait1 #endif nor_init_start: /* gpmc init */ bl cpy_nor_gpmc_code /* copy nor gpmc init code to sram */ mov r0, pc add r0, r0, #12 /* 12 is for next three instructions */ mov lr, r0 /* gpmc init code in sram should return to s_init_start */ ldr r0, sram_pc_start mov pc, r0 /* transfer ctrl to nor_gpmc_init() in sram */ #endif s_init_start: mov r0, r10 /* passing in_ddr in r0 */ bl s_init
/**************************************************************************/
s_init在board/embest/devkit8600/evm.c中定义,
/**************************************************************************/
/* back to arch calling code */ mov pc, r6 /* the literal pools origin */ .ltorg #ifdef CONFIG_NOR_BOOT cm_alwon_ocmc_0_clkstctrl_addr: .word CM_ALWON_OCMC_0_CLKSTCTRL cm_alwon_ocmc_0_clkctrl_addr: .word CM_ALWON_OCMC_0_CLKCTRL #ifndef CONFIG_AM335X cm_alwon_ocmc_1_clkstctrl_addr: .word CM_ALWON_OCMC_1_CLKSTCTRL cm_alwon_ocmc_1_clkctrl_addr: .word CM_ALWON_OCMC_1_CLKCTRL #endif #endif SRAM_STACK: .word LOW_LEVEL_SRAM_STACK _mark1: .word mark1 _lowlevel_init: .word lowlevel_init _s_init_start: .word s_init_start
/* * early system init of muxing and clocks. */ void s_init(void) { /* Can be removed as A8 comes up with L2 enabled */ l2_cache_enable(); /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ __raw_writel(0xAAAA, WDT_WSPR); while(__raw_readl(WDT_WWPS) != 0x0); __raw_writel(0x5555, WDT_WSPR); while(__raw_readl(WDT_WWPS) != 0x0); #ifdef CONFIG_SPL_BUILD /* Setup the PLLs and the clocks for the peripherals */ pll_init();
/**************************************************************************/
pll_init在board/embest/devkit8600/pll.c中定义
/**************************************************************************/
/* UART softreset */ u32 regVal; u32 uart_base = DEFAULT_UART_BASE; enable_uart0_pin_mux();
/**************************************************************************/
enable_uart0_pin_mux在board/embest/devkit8600/mux.c中定义
/**************************************************************************/
/* IA Motor Control Board has default console on UART3*/ /* XXX: This is before we've probed / set board_id */ if (board_id == IA_BOARD) { uart_base = UART3_BASE; } regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET); regVal |= UART_RESET; __raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) ); while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) & UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK); /* Disable smart idle */ regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET)); regVal |= UART_SMART_IDLE_EN; __raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET)); /* Initialize the Timer */ init_timer();
/**************************************************************************/
init_timer在本源码文件中定义
/**************************************************************************/
preloader_console_init();
/**************************************************************************/
preloader_console_init在arch/arm/cpu/armv7/omap-common/spl.c中定义
uboot启动时,打印的第一个信息,就是它打印的
/**************************************************************************/
config_am335x_ddr();
/**************************************************************************/
enable_uart0_pin_mux在本源码文件中定义
/**************************************************************************/
#endif }
参考: