SystemVerilog和VHSIC

The logic type was introduced in SystemVerilog. It supersedes the reg type, which was a perennial [长久的, 多年生的] source of confusion in Verilog. logic should be used everywhere except on signals with multiple drivers. Signals with multiple drivers are called nets.

Universities are almost evenly split on which of these languages is taught in a first course. Industry is trending toward SystemVerilog, but many companies still use VHDL, so many designers need to be fluent in both.

library IEEE; use IEEE.STD_LOGIC_1164.all;
  entity sillyfunction is port(a, b, c: in STD_LOGIC; y: out STD_LOGIC);
end;

architecture synth of sillyfunction is
begin
  y <= (not a and not b and not c) or
   (a and not b and not c) or
   (a and not b and c);
end;

我觉得VHDL有COBOL范，多用is这样的单词，可读性就好了？倘若如此，何不let y be而不是y <= ?

各种搞中文语言的还没有来折腾VHDL。

Compared to SystemVerilog, VHDL is more verbose and cumbersome, as you might expect of a language developed by committee. C++有委员会喽。

Both languages are fully capable of describing any hardware system, and both have their quirks. The best language to use is the one that is already being used at your site or the one that your customers demand. Most CAD/EDA tools today allow the two languages to be mixed so that different modules can be described in different languages. CAD:计算机辅助设计; EDA:电子设计自动化。

Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984. Gateway was acquired by Cadence in 1989 and Verilog was made an open standard in 1990, under the control of Open Verilog International. The language became an IEEE standard1 in 1995. The language was extended in 2005 to streamline idiosyncrasies [怪习惯] and to better support modeling and verification of systems. These extensions have been merged into a single language standard, which is now called SystemVerilog (IEEE STD 1800-2009). SystemVerilog file names normally end in .sv.

VHDL is an acronym for the VHSIC Hardware Description Language. VHSIC is, in turn, an acronym for the Very High Speed Integrated Circuits program of the US Department of Defense. VHDL was originally developed in 1981 by the Department of Defense to describe the structure and function of hardware. Its roots draw from the Ada programming language. The language was first envisioned for documentation but was quickly adopted for simulation and synthesis. The IEEE standardized it in 1987 and has updated the standard several times since. This chapter is based on the 2008 revision of the VHDL standard (IEEE STD 1076-2008), which streamlines the language in a variety of ways. To use VHDL 2008 in ModelSim, you may need to set VHDL93=2008 in the modelsim.ini configuration file. VHDL file names normally end in .vhd.

我英语不行，所以我觉得set VHDL_VERSION=2008更好懂。

六级/考研单词: logic, confuse, multiple, fluent, entity, hardware, streamline, verify, merge, norm, integrate, synthesis, update, revise, configuration