多发射和流水线是啥关系？

https://www.cs.umd.edu/~meesh/cmsc411/CourseResources/CA-online/chapter/multiple-issue-processors-i/index.html

...The ideal CPI (Clock Per Instruction) that we can expect in a pipelined implementation is only 1. If we want to further reduce CPI, we need to explore the option of issuing and completing multiple instructions every clock cycle. For example, if we issue and complete two instructions every clock cycle, ideally we should get a CPI of 0.5. Such processors are called multiple issue processors...

UMD: 马里兰大学，The University of Maryland.

经过二十年不懈的努力，人们似乎止步于0.5了 :-)  

二十年Architecture之长进

The highest and lowest BogoMips ratings (tldp.org)

https://wikimili.com/en/Intel_8088

80x86 Integer Instruction Set Timings (8088 - Pentium) (maine.edu)

CPU2017 Integer Rate Result: Dell Inc. PowerEdge R840 (Intel Xeon Platinum 8168, 2.70 GHz) (spec.org)

 From lscpu:
      Architecture:          x86_64
      CPU op-mode(s):        32-bit, 64-bit
      Byte Order:            Little Endian
      CPU(s):                96
      On-line CPU(s) list:   0-95
      Thread(s) per core:    2
      Core(s) per socket:    24
      Socket(s):             2
      NUMA node(s):          4
      Vendor ID:             GenuineIntel
      CPU family:            6
      Model:                 85
      Model name:            Intel(R) Xeon(R) Platinum 8168 CPU @ 2.70GHz
      Stepping:              4
      CPU MHz:               2693.677
      BogoMIPS:              5387.35