R2ISC

VLIW, Very Long Instruction Word, 超长指令字的大概其意思是：编译器优化汇编代码，把比如4条可以同时执行的指令搞成一条Very Long指令。如果只找到了2~3条，就插入2~1条NOP指令。很自然地，指令/机器码F0表示可以并行，后面来一堆指令，再来条F1表示结束并行，应该也行啊。

本来想恶搞个名词Variable Length Instruction Word，发现这个不仅真有，而且人们已经试过了不好使，甚至还造了EPIC (Explicitly Parallel Instruction Computing)这个词。我甚至觉得我是先看到别人的，再自以为自己也想到了。毫不气馁地再造个词：R²ISC，Really RISC，是啥最后说。

Explicitly Parallel Instruction Computing. The HP/Intel term for a form of VLIW with Variable Length Instruction Groupings which uses fields in the instruction stream or instructions themselves to group (specify instruction dependencies), rather than using a fixed length instruction word. Used in the TI 320C6x and the HP/Intel Merced/IA/64. Two problems are usually identified with VLIW processors (like the Phillips TriMedia). One is that if the instruction word can't be filled, the rest of the entries need to be filled with NOP instructions, which waste space. The other is that it prevents future versions which may be able to execute more instructions in parallel, or lower cost versions which execute fewer. EPIC solves this, but requires a small semantic change that instructions within a group must be independent - that is, act the same whether they were executed in order or parallel. By contrast, in the MultiFlow TRACE systems a pair of instructions such as "MOVE A, B" and "MOVE B, A" could be in the same word because they were guaranteed to execute in parallel, with the result that values in A and B would be swapped.

History of Itanium

In 1989, HP determined that the Reduced Instruction Set Computing (RISC) architectures were approaching the processing limit at one instruction per cycle. HP researchers investigated a new architecture, later named Explicitly Parallel Instruction Computing (EPIC), that allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, in which a single instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel.[5] The goal of this approach is twofold: to enable deeper inspection of the code at compile time to identify additional opportunities for parallel execution, and to simplify the processor design and reduce energy consumption by eliminating the need for runtime scheduling circuitry.

HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake the very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.

During development, Intel, HP, and industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computing (CISC) architectures for all general-purpose applications. Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures respectively in favor of migrating to IA-64.

Several groups ported operating systems for the architecture, including Microsoft Windows, OpenVMS, Linux, HP-UX, Solaris, Tru64 UNIX, and Monterey/64. The latter three were canceled before reaching the market. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery timeframe of Merced began slipping.

Intel announced the official name of the processor, Itanium, on October 4, 1999.

Within hours, the name Itanic had been coined on a Usenet newsgroup, a reference to the RMS Titanic, the "unsinkable" ocean liner that sank on her maiden voyage in 1912. "Itanic" has since often been used by The Register, and others, to imply that the multibillion-dollar investment in Itanium—and the early hype associated with it—would be followed by its relatively quick demise. HP的忆阻器还没有拿出来。

C++标注库开始支持barrier了。Linux kernel的源代码里手工指明哪个分支可能性大。

R²ISC多两条intrinsic: __epic_begin__和__epic_end__，觉得程序不够快就找到最内层循环/高频被调用函数，无脑地在函数的最前面__epic_begin__，最后面__epic_end__，编译一测试发现不对，就再来一对，缩小范围/粒度。这种优化比改进排序/搜索省脑多了, RR是RenRou(人肉)的首字母 :-) 纯属恶搞。

六级/考研单词: instruct, invariable, epic, implicit, parallel, compute, execute, trace, swap, investigate, multiple, implement, elaborate, shallow, inspect, compile, eliminate, derive, undertake, manufacture, initiate, dominate, desktop, silicon, abandon, farther, respective, migrate, latter, liner, maiden, voyage, seldom, invest, intrinsic

HP zx6000 system board with dual Itanium 2 processors:

散热器很漂亮。