VLIW and Superscalar

Very Long Instruction Word (VLIW) is used to describe an assembly language instruction set implemented using horizontal microcode. A horizontally encoded instruction word which encodes four or more operations might be considered "very long".

VLIW architectures are sometimes classified as a type of static superscalar architecture. They are static in the sense that which units operate in parallel is determined by the instruction rather than by dynamic scheduling at run time.

Producing code for VLIW machines is difficult; trace scheduling is a helpful compiler technique.

The most famous VLIW machine was built by (the late) Multiflow Computer, Inc.

Horizontal microcode is microcode using horizontal encoding. Horizontal encoding (processor) is an instruction set where each field (a bit or group of bits) in an instruction word controls some functional unit or gate directly, as opposed to vertical encoding where instruction fields are decoded (by hard-wired logic or microcode) to produce the control signals. Horizontal encoding allows all possible combinations of control signals (and therefore operations) to be expressed as instructions whereas vertical encoding uses a shorter instruction word but can only encode those combinations of operations built into the decoding logic.

An instruction set may use a mixture of horizontal and vertical encoding within each instruction. Because an architecture using horizontal encoding typically requires more instruction word bits it is sometimes known as a very long instruction word (VLIW) architecture.

A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor that can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows for more throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit.

In Flynn's taxonomy, a single-core superscalar processor is classified as an SISD processor (Single Instruction stream, Single Data stream), though a single-core superscalar processor that supports short vector operations could be classified as SIMD (Single Instruction stream, Multiple Data streams). A multi-core superscalar processor is classified as an MIMD processor (Multiple Instruction streams, Multiple Data streams).

While a superscalar CPU is typically also pipelined, superscalar and pipelining execution are considered different performance enhancement techniques. The former executes multiple instructions in parallel by using multiple execution units, whereas the latter executes multiple instructions in the same execution unit in parallel by dividing the execution unit into different phases.

The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU):

• Instructions are issued from a sequential instruction stream
• The CPU dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)
• The CPU can execute multiple instructions per clock cycle

Seymour Cray's CDC 6600 from 1966 is often mentioned as the first superscalar design. The 1967 IBM System/360 Model 91 was another superscalar mainframe. The Motorola MC88100 (1988), the Intel i960CA (1989) and the AMD 29000-series 29050 (1990) microprocessors were the first commercial single-chip superscalar microprocessors. RISC microprocessors like these were the first to have superscalar execution, because RISC architectures free transistors and die area which can be used to include multiple execution units (this was why RISC designs were faster than CISC designs through the 1980s and into the 1990s).

Except for CPUs used in low-power applications, embedded systems, and battery-powered devices, essentially all general-purpose CPUs developed since about 1998 are superscalar.

The P5 Pentium was the first superscalar x86 processor; the Nx586, P6 Pentium Pro and AMD K5 were among the first designs which decode x86-instructions asynchronously into dynamic microcode-like micro-op sequences prior to actual execution on a superscalar microarchitecture; this opened up for dynamic scheduling of buffered partial instructions and enabled more parallelism to be extracted compared to the more rigid methods used in the simpler P5 Pentium; it also simplified speculative execution and allowed higher clock frequencies compared to designs such as the advanced Cyrix 6x86.

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