Verilog里的function, loop和#define

Terminology in the electronics and computer industries can sometimes be confusing and overlapping. A Verilog funciton looks like functions in programming languages that are sometimes called procedures or methods depending on the language. However, Verilog describes hardware in a physical domain, not software in a time domain. Software functions physically create on instance of the code that is called multiple times. Hardware functions, whether in Verilog, VHDL, or another hardware description lanauge, create a physical instance for each time the function is "called.". From a software perspective, Verilog functions are more like software macros.

上面是从一本书里抄来的。我觉得说的挺精辟，但有瑕疵。与其说each time the function is called, 不如说each place the function is called. 比如:

for (int i = 0; i < 1000; i++) some_func(); 

some_func被调用1000次，调用它的地方只有一个。

for (int i = 0; i < 32; i++)  c[i] = b[i] + a[i]; 是软件里的循环，Verilog里也可以写for循环，本例的电路实现可以是32个加法器同时加。软件耗时间换成了硬件耗空间。SIMD指令同时加比如16个byte，像是两者的结合。硬件可以选择用4个,8个，或16个加法器。据说CPU里有微码，微码"解释执行"机器码。SIMD指令与for循环相比，起码省了些"编译"(译码)时间。

Verilog里还可以`define AND asdp (4'b0000, // [Rd] = [Rn] AND (2nd operand)

asdp是个task，而task不是软件工程师倾向于理解的task，而是返回多个值的函数：

task will be introduced in Chapter 10 that is similar to the function command (又来了，啥叫函数命令?!), but it provides for multiple outputs.

六级/考研单词: electron, compute, confuse, overlap, hardware, physics, domain, multiple