Logic Synthesis for FPGA
作者: Rajeev Murgai, Robert K. Brayton, Alberto Sangiovanni-Vincentelli.
Recently, user-programmable gate arrays, called field-programmable gate arrays (FPGAs), have emerged and are changing the way electronic systems are designed and implemented. FPGA chips are prefabricated as arrays of identical programmable logic blocks with routing resources, and are configured by the user into the desired circuit functionality. The most popular FPGA architectures use either a look-up table (LUT) or a multiplexor-configuration as the basic building block.
Conventional synthesis approaches fail to produce satisfactory solutions for FPGAs, since the constraints imposed by FPGA architectures are quite different. FPGA synthesis is a rapidly growing area of research.
When faced with the task of designing the next generation processor, the designers of company A first come up with a system description of the processor. It includes detailed description of the instruction set, the interface with the external world, design objectives and constraints, etc. Then, using years of expertise in integrated-circuit design, they produce an implementation that meets the design objectives. In order to verify that th~ implementation is functionally correct (for example, on fetching.and executing an ADD instruction, the correct sum is produced), sequences of input values are applied, and it is checked if the desired outputs are generated. Very likely, the processor is a huge and complex design, and so cannot be tested exhaustively. After achieving a reasonable degree of confidence in the correctness, the designers send the design for fabrication. In due time, say a month, the chip comes back from the foundry and is tested again to verify that it works as expected. This time it is much faster to simulate the same set of test vectors, so many more can be used and more functionality can be tested for. If the chip fails, it is due to either a manufacturing defect, in which case the chip is discarded, or the non-exhaustive testing done earlier on. If the latter, the faulty part of the circuit is identified and fixed and the modified design is resent for fabrication.
Consider another scenario in which the chip passes all the tests, but during the fabrication, it is decided that one new instruction should be added to the instruction set. The design-fabrication-test cycle has to be repeated here as well. After some iterations, the processor chip is finally ready to be shipped - however, the entire cycle may have taken a year or two.
With the growing complexity of the digital circuits, doing a design completely manually is cumbersome and slow and is out of question.
Design Specification: The desired behavior of the system is specified at some level of abstraction.
High-level Design: This stage transforms the design specification into a description that uses memories, adders, register files, controllers, etc. This description is called the register-transfer level, or RTL, description. If the design is too big, it is partitioned into smaller pieces to reduce the overall complexity. This step corresponds to generating the Boolean equation specifying the dependence of out on inputs a and b.
Logic Design: The RTL description is first optimized for an objective function, such as minimum chip area, meeting the performance constraints, low power, etc. This step is called logic optimization. The optimized representation is then mapped to some primitive cells present in a library. This final implementation is in terms of interconnections of gates, functional units, and registers. For the comparator, a simple interconnection of gates of the library is obtained.
Physical Design: The locations of various modules on the chip are determined (placement), and the interconnections of the circuit are routed between or through the placed modules. Also, the pad locations for inputs and outputs are determined in this step. The final layout is sent for fabrication.
The user-programmable or field-programmable hardware devices are prefabricated as arrays of identical programmable logic blocks with routing resources, and are configured by the user into the desired circuit functionality. The configuration (or programming) time is small - of the order of minutes.
A PLA (Programmable Logic Device) has two planes - an AND plane and an OR plane. The AND plane implements the product terms and the OR plane realizes their OR.
FPGAs have more fine-grain logic blocks or gates. The basic FPGA architectures share a common feature: repeated arrays of identical logic blocks.
The basic block of an LUT architecture is a look-up table that can implement any Boolean function of up to m inputs, m >= 2. In n commercial LUT -based architectures, each basic block has one or more LUT s, along possibly with other logic elements (such as flip-flops, fast carry logic, etc.).
In the MUX-based architectures, the basic block is a configuration of multiplexors, with possibly a few additional logic gates such as ANDs and ORs.
The interconnections between the blocks have to be programmed in order to realize the desired circuit connectivity. Interconnect can be either reprogrammable or one-time programmable.
The main constraints in synthesizing circuits onto these architectures are:
1. a limited number of logic blocks on a chip,
2. the functionality of the block, i.e., what functions can be put on a block,
3. limited wiring resources, which often determine how much logic can be placed on a chip, and
4. interconnect delays are significant and cannot be ignored during synthesis.
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