Robert Brayton and the Espresso algorithm

Minimizing Boolean functions by hand using the classical Karnaugh maps is a laborious, tedious and error prone process. It isn't suited for more than six input variables and practical only for up to four variables.

The first alternative method to become popular was the tabular method developed by Willard Quine and Edward McCluskey.

Although this Quine-McCluskey algorithm is very well suited to be implemented in a computer program, the result is still far from efficient in terms of processing time and memory usage. Adding a variable to the function will roughly double both of them, because the truth table length increases exponentially with the number of variables.

The Espresso logic minimizer is a computer program using heuristic and specific algorithms for efficiently reducing the complexity of digital logic gate circuits. Espresso was developed at IBM by Robert K. Brayton. Richard L. Rudell later published the variant Espresso-MV in 1986 under the title "Multiple-Valued Logic Minimization for PLA Synthesis". Espresso has inspired many derivatives.

Robert Brayton was a member of the Mathematical Sciences Department of the IBM T. J. Watson Research Center until he joined the EECS Department at Berkeley in 1987.

The Espresso algorithm was developed by Brayton et al. at the University of California, Berkeley.

Rather than expanding a logic function into minterms, the program manipulates "cubes", representing the product terms in the ON-, DC-, and OFF- covers iteratively. Although the minimization result is not guaranteed to be the global minimum, in practice this is very closely approximated.

The Espresso algorithm proved so successful that it has been incorporated as a standard logic function minimization step into virtually any contemporary logic synthesis tool. For implementing a function in multi-level logic, the minimization result is optimized by factorization and mapped onto the available basic logic cells in the target technology, whether this concerns an field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

The original Espresso program is available as C source code from the University of California, Berkeley website. The last release was version 2.3 dated 1988. The Espresso-ab and eqntott (equation to truth table) program, an updated version of Espresso for modern POSIX systems, is available in Debian Linux distribution (.deb) file format as well the C source code. The last release was version 9.0 dated 2008.

Logic Friday is a free Windows program that provides a graphical interface to Espresso, as well as to misII, another module in the Berkeley Octtools package.

Minilog is a free Windows program that provides logic minimization exploiting the Espresso algorithm.

Robert Brayton received the BSEE degree from Iowa State University in 1956 and the Ph.D. degree in mathematics from MIT in 1961. He was a member of the Mathematical Sciences Department of the IBM T. J. Watson Research Center until he joined the EECS Department at Berkeley in 1987. He held the Edgar L. and Harold H. Buttner Endowed Chair and is currently the Cadence Distinguished Professor of Electrical Engineering at Berkeley. He is a member of the National Academy of Engineering, and a Fellow of the IEEE and the AAAS. He received the 1991 IEEE CAS Technical Achievement Award, the 1971 IEEE Guilleman-Cauer award, the 1987 ISCAS Darlington award. In 2000, he received the 2000 CAS Golden Jubilee and the IEEE Millennium Medals, the 2002 Iowa State University Marston Medal, and in 2006, the IEEE Emanuel R. Piore, the ACM Kanallakis and the EDAA Lifetime Achievement Awards. In 2007 he received the EDAC/CEDA Phil Kaufman Award and in 2009, the SIGDA/CEDA A. Richard Newton Technical Impact Award. He has authored over 450 technical papers, and 10 books in the areas of the analysis of nonlinear networks, simulation and optimization of electrical circuits, logic synthesis, and formal design verification. https://www2.eecs.berkeley.edu/Faculty/Homepages/brayton.html  Espresso (berkeley.edu)

Robert K. Brayton: free download. Ebooks library. On-line books store on Bookzz

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_memset:    /* DAMN ULTRIX for inefficient memset */
    .word 0
    movc5    $0,(sp),8(ap),12(ap),*4(ap)
    movl    4(ap),r0
    ret

/*  Yes, I know this routine is a mess */
void read_cube(fp, PLA)
register FILE *fp;
pPLA PLA;

/*  Hack for backward compatibility (ACK! ) */
backward_compatibility_hack(argc, argv, option, out_type)