A PCI Express to PCIX Bridge optimized for performance and area

https://dspace.mit.edu/handle/1721.1/16674

The core is approximately 27K gate count, runs at a maximum of 250 MHz, and is synthesized to a current standard technology.

The verification portion of this thesis posed quite a challenge. The Bridge implementation ended up with 1150 input ports and 1061 output ports due to the interfaces of the vendor’s PCI Express and PCIX Interfaces. With only one person to create a verification environment from scratch, a hierarchical approach was taken to find errors early since bugs are difficult to find and fix at the system level.

A Design Compiler was used to synthesize the PCIEXB Verilog code into a gate-level netlist targeting a current IBM ASIC technology.

Synthesizing the Bridge involved making TCL scripts that were read by the Design Compiler.

A Verilog netlist representation of the Bridge is the final result of the synthesis.

Many inexperienced engineers often run into problems with synthesis during their first design project. Knowing this is the case, efforts were made to fix these mistakes early on in the development process. 1. Combinational logic was coded in assign statements rather than in an always block for multiple reasons; 2. Synthesize Early and Often.

和开发软件还是有相像之处的：1. 不要留下没初始化的变量，但不要在for循环的内层memset(ary, 0, 1GB); 2. Debug/Run earyly and often, 不要"我的程序Debug模式没错，Release模式一运行就crash，总共就7~8000行，你帮我解决下……" 装个Runtime Service Pack; Link的时候keep reference…… 还真能解决，不算麻烦。可怕的是它有时crash有时不，算出来的矩阵识别率差点意思…… 不再干这行，我太幸福了！！！:-)