数字电路基础知识

https://www.tutorialspoint.com/digital_circuits/index.htm

Number Systems, Base Conversions, Binary Numbers Representation, Signed Binary Arithmetic, Codes, Error Detection & Correction Codes, Boolean Algebra, Canonical and Standard Forms, K-Map Method, Quine-McCluskey Tabular Method, Logic Gates, Two-Level Logic Realization, Combinational Circuits

[LDOCE][牛津] the canon of Holy Scripture:《圣经》的真经; canonical是canon的形容词，不是cannon(大炮)的。
canonical: 1. according to canon law; 2. in the simplest mathematical form

Arithmetic Circuits

Half adder is a combinational circuit, which performs the addition of two binary numbers A and B are of single bit. We can implement its functions with 2-input Ex-OR gate & 2-input AND gate. function: 功能; 函数 Ex-OR, XOR: Exclusive OR. ex-wife的ex-: Latin 'out of, from'

Full adder performs the addition of three bits A, B and Cin. Where, A & B are the two parallel significant bits and Cin is the carry bit, which is generated from previous stage. carry: 多出来的位要 携带, 搬运, 传送, 运送。A 4-bit binary adder performs the addition of two 4-bit numbers.

We can implement any higher order binary adder just by cascading the required number of Full adders. (C0=0). This binary adder is also called as ripple carry binary adder because the carry propagates ripples from one stage to the next stage.

The subtraction of two binary numbers A and B can be written as, A - B = (2′s complimento f B) = A + (1′s compliment of B) + 1. To get 1's complement of a binary number, invert the given number. To get 2's complement of it, invert it and add 1 to the least significant bit (LSB) of given result. For example:
3 - 2 = 011 - 010 = 011 + 101 + 001 = 001
2 - 3 = 010 + 100 + 001 = 111 (-1)
or:
2 - 3 = 2 + (-3) = 010 + (~011 + 001)

So the operation of a subtractor is similar to that of an adder internally. (C0=1)

complement(ary) angle: 余角(90°), supplement(ary) angle: 补角，The inverse of a number is defined as the number created by interchanging the face value (from left to right) and index of digits of number, The opposite of a number is a number that is the same distance from 0 as another number, but in the opposite direction. Given a number, the opposite of that number can also be thought of as the number that needs to be added in order for the result to be 0, The reciprocal of any quantity is, one divided by that quantity.

Decoder is a combinational circuit that has 'n' input lines and maximum of 2^n output lines. One of these outputs will be active High based on the combination of inputs present, when the decoder is enabled. That means decoder detects a particular code. 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. One of these four outputs will be '1' for each combination of inputs when enable, E is '1'. An Encoder is a combinational circuit that performs the reverse operation of Decoder.

Multiplexer has maximum of 2^n data inputs, 'n' selection lines and single output line. One of these data inputs will be connected to the output based on the values of selection lines. 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. 从内部接线来看，input和output可能connect着。把Multiplexer看作个黑盒子或者C语言里的函数，那么数据从input pass到output.

De-Multiplexer performs the reverse operation of Multiplexer. It has single input, 'n' selection lines and maximum of 2^n outputs. The input will be connected to one of these outputs based on the values of selection lines. 1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1 &Y0. invert, inverse, revert, reverse有何不同？前文翻转二进制位用了invert，此段功能颠倒用了reverse. [柯林斯] Inverted commas are punctuation marks that are used in writing to show where speech or a quotation begins and ends. They are usually written or printed as `'". [LDOCE] If a vehicle or its driver reverses, they go backwards.

Programmable Logic Devices (PLDs) are integrated circuits. They contain an array [不要看到array就想到数组。 陈列, 一系列, 部署] of AND gates and another array of OR gates. There are three kinds of PLDs based on the type of array(s), which has programmable feature.
1. Programmable Read Only Memory (PROM)
2. Programmable Array Logic (PAL)
3. Programmable Logic Array (PLA)

Memory里存逻辑听起来别扭，真值表顺耳。
function buy_a_new_phone(have_money, too_old, lost) { return have_money && (too_old || lost) }
function buy_a_new_phone(i, j, k) { static const bool tbl[2][2][2] = { ... }; return tbl[i][j][k]; }
函数可以返回32/64位的int，估计硬件可以"return" 7~80位。组合爆炸，2^32=40亿。
版本1的机器代码也是串二进制位，binary information，但这种搞法好像算CPU了？We need decoders to access PLDs?

The threshold gate contains at least one input and only one output. Additionally, it contains the respective weights to each input and a threshold value. 听起来像机器学习里的神经元？https://victorzhou.com/blog/intro-to-neural-networks/
训练的时候weight要变，online用训练好的模型时才有用？

This sequential circuit contains a set of inputs and outputs. The outputs of sequential circuit depends not only on the combination of present inputs but also on the previous outputs. Previous output is nothing but the present state. Therefore, sequential circuits contain combinational circuits along with memory storage elements. Some sequential circuits may not contain combinational circuits, but only memory elements.

There are two types of memory elements based on the type of triggering that is suitable to operate it.
1. Latches, level sensitive, Set Reset (SR), Data (D)
2. Flip-flops (called a trigger circuit by IBM), edge sensitive, SR, D, JK, T
We can convert one flip-flop into the remaining three flip-flops by including some additional logic. So, there will be total of twelve flip-flop conversions.

A flip-flop can store one-bit of information. In order to store multiple bits of information, we require multiple flip-flops. The group of flip-flops, which are used to hold store the binary data is known as register.

Have you signed the hotel register? cash register: 收银机。
file: a set of papers; (存放文件公文卷宗档案等的)抽屉架子夹子封皮箱子等。

If the register is capable of shifting bits either towards right hand side or towards left hand side is known as shift register. Serial/Parallel In - Serial/Parallel Out Shift Registers. Shift registers are used as Parallel to serial converters, Serial to parallel converters, Sequence generators, and Counters. The Serial In - Parallel Out SIPO shift register accepts the data from outside in serial form and it requires 'N' clock pulses in order to shift 'N' bit data. Johnson Ring counter is also called as Twisted Ring counter and switch tail Ring counter.

Synchronous sequential circuits change affect their states for every positive ornegative transition of the clock signal based on the input. So, this behavior of synchronous sequential circuits can be represented in the graphical form and it is known as state diagram. A synchronous sequential circuit is also called as Finite State Machine FSM, if it has finite number of states.

Regular expressions describe patterns which can be recognized by finite state machines (FSM). It is possible to algorithmically construct a FSM that corresponds to a given regular expression. A FSM can be described by a transition table (program), which can be represented by a string.

"What is the difference between finite automata and finite state machines?" [stackexchange] In FSM for circuit designs the input signal is mostly assumed to be a bit (binary), whereas in finite state automata one can have a general "abstract" alphabet of input symbols.
"What is a Truing machine?" https://introcs.cs.princeton.edu/java/52turing/

There are two types of FSMs.
1. Mealy State Machine, outputs depend on both present inputs & present states.
2. Moore State Machine, outputs depend only on present states.

Microprocessor technology has dramatically changed since 1971, when Intel's 4004 CPU ran at a mere 740 KHz and contained only 2,250 transistors using a 10 micrometer process. [不算内存？]

"Intel 4004 simulator/emulator", 我记得有个在屏幕上显示电路图，电线会变红的，Java写的，但找不着了。我记得很清楚的是：我没看懂。:-)

六级/考研单词: convert, arithmetic, detect, algebra, logic, holy, script, cannon, accord, mathematics, implement, parallel, propagate, subtract, compliment, complement, invert, reverse, data, comma, integrate, array, static, threshold, respective, blog, offline, thereby, trigger, multiple, serial, pulse, twist, affection, transition, diagram, finite, regulate, construct, correspond, differentiate, abstract, alphabet, mere, transistor, ax, halt

abacus [Date: 1300-1400; Language: Latin; Origin: Greek 'flat piece of stone']
compute [Date: 1600-1700; Language: Latin; ... 'to think']
calculate: [Date: 1500-1600; Language: Latin; Origin: ... from calculus 'stone used in counting']
suanpan: [Origin: Chinese, "Isn't that obvious?"]
kowtow词典里有，TBBT里老外也说。congee, wok ...

1001如何？64位内存(ENIAC 200个word; byte: a biteful of bits). 4条8位的定长指令，数据宽度5位，最高位为符号位，jlz: 小于0则跳转。所谓内存，用Latch来搭，the /ðiː/ register. ax, cx, c, ip (instruction pointer)都是它部分位的别名。

虽然下面犯了许多错误，我还是编了个程序的：1001-asm-imitator.py - Fun_with_Words - 博客园 (cnblogs.com)

2~3个寄存器，7~8条指令，按时钟单步，高电平的线用红色显示。下面是我能做的；
mov ax, 1
mov cx, 9
add ax, 1
add cx, -1
jlz -2 ; 向上跳两条指令。-16位也行？
halt

上面是胡说，接着再八道。电脑是怎么think的？不对此有点了解，觉得自己在玩真空中的球形鸡。不考虑电气等因素，专注于逻辑。level sensitive的Latch适合我们，可显示为个黑盒子:
byte access_register(byte addr) { return fake[addr]; } 或者分成两个bank { return (bank0[addr] << 4) | bank1[addr]; }, 或者每个bank 1位，电路图上就不要显示内部了。上电后CPU并不开始run，而是可以搬动开关设置reigster: init_register(byte data[16]); 然后hit the button: while(1) on_clock();
function on_clock() {
for (;;)
if (all gates are refreshed) break
for g in all_gates:
if (g.refreshed) continue;
if (g所依赖的，或者说g的输入是它的输出的, gate们 都refresh了) g.on_clock();

Five_bits_Full_adder::on_clock() { out = in0 + in1; refreshed = 1; } // 知道加法器的原理后把它当黑盒子用就好了，也别显示内部。

function connect(gate_out, pin_out, gate_in, pin_in) // 生成网表，记录依赖关系(图?)

the register的每一位用个灯，或者显示1/0，最好像那种钟表，一个轮子上印着0和1，声效像机场通知牌。

然后设计个语言VSLI (Very Simple Logic Indeed)，用flex和bison给它做个stuff，能把用像Verilog那样的语言描述的stuff变成仿真器/模拟器要用的stuff. 当然Verilog和VSLI天差地别，而且前者说不定能导出网表，但不会是txt格式吧？不用VSLI而是C++也行，但我觉得会有许多啰嗦的语句描述pin属于哪个gate. VSLI的好处还有：还可以用它设计别的CPU啊，比如程序和数据分开的哈弗架构？

汇编器不用做，我可以手撕汇编和机器码，做点力所能及的事。

mov ax, 1 00 0 00001
mov cx, 9 00 1 01001
add ax, 1 01 0 00001
add cx, -1 01 1 11111
jlz -2 10 11110 ; 哦哦，忘了没有reg_idx, 那用位吧，可以省几个移位寄存器。
halt 11 000000

把Latch作为整体回避了循环依赖问题。avoid, eschew.

# AndGate
in A, B
out C
[C=A+B]

上面描述了一个器件，#长得就像个长脚的盒子, [盒子里的逻辑]。也可以：
#0
AB
1
[1=+AB]

0类器件有两个输入，一个输出，表达式用波兰式，这样的格式可以手撕。

> AndGate.1.C OrGate.3.A
> 0.0.2 1.0.0
第1个AndGate的C接3号或门的A，前者输出，后者输入。

我们这个initiative，能挣8个月到88岁的人的钱，请耐心往下看。软件免费送，卖硬件。48位的程序，软件有按钮可以改（起码可以改改数)，硬件不显示(写死)。ax, cx共10位，软硬件都显示。按clock单步，软件显示接线上的高电平（可调速度），硬件不显示。硬件可以取巧：按一下按钮把灯显示对就行了，你管我内部怎么实现。每执行一条指令，机器就转移下状态。4条指令不是4个状态，而是多个。人不能两次跨过同一条河流，add ax, 1会执行多次。粉灯版卖给女宝宝，蓝灯版男宝宝，机械版，镀金版，地鼠版 [我家孩子8个月就会调程序了:-)] 中学可以拿它做教具，对着程序讲，硬件增加48个开关。书《如何手撕CPU》。面包板、万用表、示波器、逻辑分析仪——给卖这些个的收费带货。不卖嘎，卖知识。这个能卖到全世界。Together, we coin the word suanpan. 醋有了，就等饺子了。:-)

gate_1_C = gate_1_A + gate_1_B

gate_2_A = gate_1_C
...
那岂不是就剩两步：1. 写哪些赋值语句; 2. 以什么样的顺序执行。在python或javascript里eval()下？

对我来说，把指令放在ROM里比寄存器里反而好理解点。访问内存时，CPU的一个cycle需要几个clock. 

def read_mem(a7, a6, a5, a4, a3, a2, a1, a0): reurn rom[.....]; 每个数组元素是个8位的tuple，试了下写起来好累。

CPU应该也算个状态机。fetch_instruction: a7 = x; a6 =x ; ... a0=x; 硬件是8根线一起过去。然后放在latch里？译码用decoder? "算术单元"得有根enable线？enable时才加，线是始终接着的？way out of my league啊。Search(the Simplest CPU design)，学习中…… program counter怎么设初值呢？得和reset线接在一起吧：a=!reset & (....), reset是1是必为0, reset是0时没影响。b=reset | (...), reset是1时必为1。re-set里面有个set，头一次是set，以后是set again. 是不是得有个“内部总线”? 手工调整赋值语句顺序，仿真器不必解决依赖关系?

哦，少了条jmp指令啊，so humiliating, embarrassing. 嗯，hlt改jlz 0, 哦，还有别的错误……