随笔分类 -  suanpan

摘要:“技多不压身”。内卷时代对编译和虚拟机技术有所了解是极好的。可是JVM太庞大了。 这个 虽然只有10KB,但它包含玩具级C编译器和x86虚拟机,阅读它可以快速入门,当然门楣很高:-)。 它是 基本能看懂的C编译器 的改进版,混合使用了自顶向下和自底向上(bison)分析。 ① 你可以为它增加do语句 阅读全文
posted @ 2023-01-07 00:08 Fun_with_Words 编辑
摘要:Fabrice Bellard is a French computer programmer known for writing FFmpeg, QEMU, and the Tiny C Compiler 和许许多多别的。 我修改了下他写的otccelfn.c,增加/删除了一点功能,提高了可读性。 阅读全文
posted @ 2023-01-02 22:24 Fun_with_Words 编辑
摘要:ENIAC /ˈiniæk/ or /ˈeniæk/ Electronic Numerical Integrator And Computer. EDVAC (Electronic Discrete Variable Automatic Computer) was one of the earlie 阅读全文
posted @ 2022-08-10 11:58 Fun_with_Words 编辑
摘要:The suanpan (simplified Chinese: 算盘; traditional Chinese: 算盤; pinyin: suànpán), is an abacus of Chinese origin first described in a 190 CE book of the 阅读全文
posted @ 2022-03-07 23:17 Fun_with_Words 编辑
摘要:The first programmable computers for commercial sale, such as the UNIVAC I and the IBM 701 included features to make their operation simpler. They typ 阅读全文
posted @ 2022-02-18 23:53 Fun_with_Words 编辑
摘要:假设a和b都是8位二进制数,selection是1位,什么样的器件可以从a和b中选一个出来? 好像只好用8个2-1 multiplexer,它们的sel都是selection. 每个multiplexer都可以写个真值表出来,内部用门电路实现。 不知道能否用更底层的电路,如"继电器"、"干簧管"、" 阅读全文
posted @ 2022-02-05 08:13 Fun_with_Words 编辑
摘要:一本讲FPGA的书里说:Because of complexity, the division operator cannot be synthesized automatically. We use an FSMD to implement the long-division algorithm 阅读全文
posted @ 2022-01-09 20:08 Fun_with_Words 编辑
摘要:TinyEMU (bellard.org) is a system emulator for the RISC-V and x86 architectures. Its purpose is to be small and simple while being complete. RISC-V vs 阅读全文
posted @ 2022-01-08 19:09 Fun_with_Words 编辑
摘要:Verilator is the fastest Verilog/SystemVerilog simulator. Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the sp 阅读全文
posted @ 2022-01-08 09:36 Fun_with_Words 编辑
摘要:我原以为就是个理念,没想到上网一搜,实物不少,似乎挺靠谱的。 RISC-V学习总结之历史与现状 - 冷冷北极 - 博客园 RISC-V生态架构浅析(认识RISC-V) - petercao - 博客园 RISC-V引入了Chisel: Constructing Hardware In a Scala 阅读全文
posted @ 2022-01-07 21:40 Fun_with_Words 编辑
摘要:>和==可以减完后判断符号位或是否全0。一般地,不能一上头把a,b,c和m,n都当输入来列真值表,比如它们都是32位。 阅读全文
posted @ 2022-01-06 13:08 Fun_with_Words 编辑
摘要:According to the Verilog standard, the execution of two always blocks can be scheduled in any order. This is known as a race condition. 比如我们想交换reg a和b 阅读全文
posted @ 2022-01-05 13:00 Fun_with_Words 编辑
摘要:当wire[3:0] a;时,assign y = | a; 和 assign y = a[3] | a[2] | a[1] | a[0]; 一样。这个叫reduction, python里有reduce和map函数。不精确地说,map对数组里的每个元素执行操作,n进n出;reduce也对每个元素执 阅读全文
posted @ 2022-01-04 23:43 Fun_with_Words 编辑
摘要:看了3个主帖: Nand Flash - 博客园 NAND Flash Memory Technology: The Basics of a Flash Memory Cell by Zachary Painter Technical Note NAND Flash 101: An Introduc 阅读全文
posted @ 2022-01-03 22:53 Fun_with_Words 编辑
摘要:From www.mentalfloss.com: The first recorded use of an introductory class being designated as "101" was in a University of Buffalo course catalog date 阅读全文
posted @ 2022-01-03 22:03 Fun_with_Words 编辑
摘要:Terminology in the electronics and computer industries can sometimes be confusing and overlapping. A Verilog funciton looks like functions in programm 阅读全文
posted @ 2022-01-03 20:32 Fun_with_Words 编辑
摘要:Computer Arithmetic and Verilog HDL Fundamentals by Joseph Cavanagh (z-lib.org).pdf Computer Architecture Tutorial Using an FPGA ARM Verilog Introduct 阅读全文
posted @ 2022-01-02 00:22 Fun_with_Words 编辑
摘要:仿真领域广大,历史悠久 A simulation is an approximate imitation of the operation of a process or system that represents its operation over time. Simulation is us 阅读全文
posted @ 2022-01-01 22:37 Fun_with_Words 编辑
摘要:如题,x是32位unsigned integer. 有Quake公式,(n+1)**2 - n**2 = 2n + 1, 即1+3=4, 4+5=9, 9+7=16 ... [说错了:Babbage difference and Quake's Fast Inverse Square Root - 阅读全文
posted @ 2021-12-31 17:18 Fun_with_Words 编辑
摘要:GitHub - lsils/benchmarks: EPFL logic synthesis benchmarks 有许多Verilog的.v文件可以下载。mem_ctrl.v 5万多行 2MB,变量名全是n+数字,几万行assign啊! Verilog里转义标识符(escaped identif 阅读全文
posted @ 2021-12-30 19:01 Fun_with_Words 编辑










 和4张牌。

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