Altera Coding Style 之 Latch

一、意料之外产生的 Latch

1、产生原因

     在有判断的组合逻辑中，分支不完整。例如，在Case和If的结构中，分支不完备，就有可能产生Latch。

     Latches have limited support in formal verification tools. Therefore, ensure that you do not infer latches unintentionally.

2、避免方法

     最好的方法是保证分支完备。

     为避免分支不完备，可以使用 full_case 属性。full_case 属性把未声明的分支看作 don’t care，不过 full_case 属于 synthesis_only 的属性，因此在仿真时，仿真工具仍然会生成 latch。

     The full_case attribute can be used in Verilog HDL designs to treat unspecified cases as don’t care (X). However, using the full_case attribute can cause simulation mismatches bacause this attribute is a synthesis-only attribute, so simulation tools still treat the unspecified cases as latches.

3、建议做法

     如果为了分支完备增加了 default case 或者增加了一个 else，建议给该分支赋值X。

     Don’t care (X) assignments on the default conditions are useful in preventing latch generation. For the best logic optimization, assign the default case or final else value to don’t care (X) instead of a logic value.

二、希望产生的 Latch

有趣的是，若是综合工具理解设计者的用意产生的 latch，这样的 latch 是不会有毛刺或者时序违规等问题的。

Synthesis tools can infer a latch that does not exhibit the glitch and timing hazard problems typically associated with combinational loops.

1、如何判断 latch 是否安全

     编译之后，report 里面有一个 User-Specified and Inferred Latches，如果某 latch 或者带反馈的组合逻辑不在其中，那么该 latch 或者 combinational loop 是不安全的。

     If a latch or combinational loop in your design is not listed in the User-Specified and Inferred Latches section, it means that is was not inferred as a safe latch by the software and is not considered glitch-free.

     All combinational loops listed in the Analysis & Synthesis Logic Cells Representing Combinational Loops table in the Compilation Report are at risk of timing hazards.

2、latch 与 FPGA 结构

     glitch-free 的 latch 是与器件结构密切相关的。

     对于 macrocell-based 的器件，比如 MAX3000 和 MAX7000，所有的 data (D-type) latch 和 set-reset (S-R) latch 都是安全的。

      对于 4-input(例如 Stratix，Cyclone系列，MAXII) 或者 6-input 的LUT器件，能否综合出安全的 latch ，与 latch 的输入信号数量有关。假如某个 latch 有5个输入，那么6输入的LUT可以综合处安全的 latch ，4输入的即不行。

       问题的原因在于：

        … If the Quartus II software cannot implement the latch with a single-LUT loop because there are too many inputs, the User-Specified and Inferred Latches table indicates that the latch is not free of timing hazards.

       还有一点应该注意的是，latch 的输入在某一时刻只能有一个发生变化。

        To ensure hazard-free behavior, only one control input can change at a time.

3、使用宏

      Quartus II integrated synthesis also creates safe latches when possible for instantiations for the LPM_LATCH megafunction.

 

最后有价值的一段话：

       … For LUT-based families, the Fitter uses global routing for control signals, including signals that Analysis and Synthesis identifies as enables. In some cases the global insertion delay may decrease the timing performance. If necessary, you can turn off the Quartus II Global Signal logic option to manually prevent the use of global signals, Global latch enables are listed in the Global & Other Fast Signals table in the Compiliation Report.