02 2015 档案

[转]TimeQuest之delay_fall clock_fall傻傻分不清楚
摘要：这篇我想分享一个之前在用TimeQuest约束双边沿模块的input delay时犯得一个错误，有人看了可能会觉得傻傻的，什么眼神，falling delay和 falling clk怎么会分不清呢，字面意思好区分，可要深究在约束里的具体含义，还得花点功夫，下面以ddio接收模块为例说明它们的含义以... 阅读全文
posted @ 2015-02-05 00:42 FPGA/DSP 阅读(1298) 评论(0) 推荐(0)
C6678 srio communication via Switch
摘要：First, I don't often give praise for support but I must say Travis, Karthik and Derek from TI have been extremely instrumental in getting my SRIO envi... 阅读全文
posted @ 2015-02-04 19:30 FPGA/DSP 阅读(1409) 评论(1) 推荐(0)