1 `timescale 1ns / 1ps
2 //////////////////////////////////////////////////////////////////////////////////
3 // Company:
4 // Engineer:
5 //
6 // Create Date: 19:06:11 01/02/2014
7 // Design Name:
8 // Module Name: k7_srio_top
9 // Project Name:
10 // Target Devices:
11 // Tool versions:
12 // Description:
13 //
14 // Dependencies:
15 //
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 //
20 //////////////////////////////////////////////////////////////////////////////////
21 module k7_srio_top(
22 k7_rstn,
23 srio_refclk_p,
24 srio_refclk_n,
25
26 p0_srio_rxn0,
27 p0_srio_rxp0,
28 p0_srio_rxn1,
29 p0_srio_rxp1,
30 p1_srio_rxn0,
31 p1_srio_rxp0,
32 p1_srio_rxn1,
33 p1_srio_rxp1,
34
35 p0_srio_txn0,
36 p0_srio_txp0,
37 p0_srio_txn1,
38 p0_srio_txp1,
39 p1_srio_txn0,
40 p1_srio_txp0,
41 p1_srio_txn1,
42 p1_srio_txp1
43 );
44
45 input k7_rstn;
46 input srio_refclk_p;
47 input srio_refclk_n;
48
49 input p0_srio_rxn0;
50 input p0_srio_rxp0;
51 input p0_srio_rxn1;
52 input p0_srio_rxp1;
53 input p1_srio_rxn0;
54 input p1_srio_rxp0;
55 input p1_srio_rxn1;
56 input p1_srio_rxp1;
57
58 output p0_srio_txn0;
59 output p0_srio_txp0;
60 output p0_srio_txn1;
61 output p0_srio_txp1;
62 output p1_srio_txn0;
63 output p1_srio_txp0;
64 output p1_srio_txn1;
65 output p1_srio_txp1;
66
67 // {{{ wire declarations ----------------
68 wire p0_log_clk;
69 wire p0_phy_clk;
70 wire p0_gt_pcs_clk;
71 wire p0_log_rst;
72 wire p0_phy_rst;
73 wire p0_sim_train_en = 0;
74
75 // signals into the DUT
76 wire p0_iotx_tvalid;
77 wire p0_iotx_tready;
78 wire p0_iotx_tlast;
79 wire [63:0] p0_iotx_tdata;
80 wire [7:0] p0_iotx_tkeep;
81 wire [31:0] p0_iotx_tuser;
82
83 wire p0_iorx_tvalid;
84 wire p0_iorx_tready;
85 wire p0_iorx_tlast;
86 wire [63:0] p0_iorx_tdata;
87 wire [7:0] p0_iorx_tkeep;
88 wire [31:0] p0_iorx_tuser;
89
90 wire p0_maintr_rst = 1'b0;
91
92 wire p0_maintr_awvalid;
93 wire p0_maintr_awready;
94 wire [31:0] p0_maintr_awaddr;
95 wire p0_maintr_wvalid;
96 wire p0_maintr_wready;
97 wire [31:0] p0_maintr_wdata;
98 wire p0_maintr_bvalid;
99 wire p0_maintr_bready;
100 wire [1:0] p0_maintr_bresp;
101
102 wire p0_maintr_arvalid;
103 wire p0_maintr_arready;
104 wire [31:0] p0_maintr_araddr;
105 wire p0_maintr_rvalid;
106 wire p0_maintr_rready;
107 wire [31:0] p0_maintr_rdata;
108 wire [1:0] p0_maintr_rresp;
109
110
111 // other core output signals that may be used by the user
112 wire [23:0] p0_port_timeout; // Timeout value user can use to detect a lost packet
113 wire p0_phy_rcvd_mce; // MCE control symbol received
114 wire p0_phy_rcvd_link_reset; // Received 4 consecutive reset symbols
115 wire p0_port_error; // In Port Error State
116 wire p0_mode_1x; // Link is trained down to 1x mode
117 wire p0_srio_host; // Endpoint is the system host
118 wire [223:0] p0_phy_debug; // Useful debug signals
119 wire p0_gtrx_disperr_or; // GT disparity error (reduce ORed)
120 wire p0_gtrx_notintable_or; // GT not in table error (reduce ORed)
121 wire [15:0] p0_deviceid; // Device ID
122 wire p0_port_decode_error; // No valid output port for the RX transaction
123 wire p0_idle_selected; // The IDLE sequence has been selected
124 wire p0_idle2_selected; // The PHY is operating in IDLE2 mode
125 wire p0_autocheck_error; // when set, packet didn't match expected
126 wire p0_port_initialized; // Port is Initialized
127 wire p0_link_initialized; // Link is Initialized
128 wire p0_exercise_done; // sets when the generator(s) has completed
129 wire p0_clk_lock; // asserts from the MMCM
130
131 // other core output signals that may be used by the user
132 wire p0_phy_mce = 1'b0; // Send MCE control symbol
133 wire p0_phy_link_reset = 1'b0; // Send link reset control symbols
134 wire p0_force_reinit = 1'b0; // Force reinitialization
135
136 wire p1_gt0_qplloutclk_i;
137 wire p1_gt0_qplloutrefclk_i;
138
139 wire p1_log_clk;
140 wire p1_phy_clk;
141 wire p1_gt_pcs_clk;
142 wire p1_log_rst;
143 wire p1_phy_rst;
144 wire p1_sim_train_en = 0;
145
146 // signals into the DUT
147 wire p1_iotx_tvalid;
148 wire p1_iotx_tready;
149 wire p1_iotx_tlast;
150 wire [63:0] p1_iotx_tdata;
151 wire [7:0] p1_iotx_tkeep;
152 wire [31:0] p1_iotx_tuser;
153
154 wire p1_iorx_tvalid;
155 wire p1_iorx_tready;
156 wire p1_iorx_tlast;
157 wire [63:0] p1_iorx_tdata;
158 wire [7:0] p1_iorx_tkeep;
159 wire [31:0] p1_iorx_tuser;
160
161 wire p1_maintr_rst = 1'b0;
162
163 wire p1_maintr_awvalid;
164 wire p1_maintr_awready;
165 wire [31:0] p1_maintr_awaddr;
166 wire p1_maintr_wvalid;
167 wire p1_maintr_wready;
168 wire [31:0] p1_maintr_wdata;
169 wire p1_maintr_bvalid;
170 wire p1_maintr_bready;
171 wire [1:0] p1_maintr_bresp;
172
173 wire p1_maintr_arvalid;
174 wire p1_maintr_arready;
175 wire [31:0] p1_maintr_araddr;
176 wire p1_maintr_rvalid;
177 wire p1_maintr_rready;
178 wire [31:0] p1_maintr_rdata;
179 wire [1:0] p1_maintr_rresp;
180
181
182 // other core output signals that may be used by the user
183 wire [23:0] p1_port_timeout; // Timeout value user can use to detect a lost packet
184 wire p1_phy_rcvd_mce; // MCE control symbol received
185 wire p1_phy_rcvd_link_reset; // Received 4 consecutive reset symbols
186 wire p1_port_error; // In Port Error State
187 wire p1_mode_1x; // Link is trained down to 1x mode
188 wire p1_srio_host; // Endpoint is the system host
189 wire [223:0] p1_phy_debug; // Useful debug signals
190 wire p1_gtrx_disperr_or; // GT disparity error (reduce ORed)
191 wire p1_gtrx_notintable_or; // GT not in table error (reduce ORed)
192 wire [15:0] p1_deviceid; // Device ID
193 wire p1_port_decode_error; // No valid output port for the RX transaction
194 wire p1_idle_selected; // The IDLE sequence has been selected
195 wire p1_idle2_selected; // The PHY is operating in IDLE2 mode
196 wire p1_autocheck_error; // when set, packet didn't match expected
197 wire p1_port_initialized; // Port is Initialized
198 wire p1_link_initialized; // Link is Initialized
199 wire p1_exercise_done; // sets when the generator(s) has completed
200 wire p1_clk_lock; // asserts from the MMCM
201
202 // other core output signals that may be used by the user
203 wire p1_phy_mce = 1'b0; // Send MCE control symbol
204 wire p1_phy_link_reset = 1'b0; // Send link reset control symbols
205 wire p1_force_reinit = 1'b0; // Force reinitialization
206
207 wire [35:0] CONTROL0;
208 wire [35:0] CONTROL1;
209 wire [35:0] CONTROL2;
210 wire [35:0] CONTROL3;
211
212 srio_clk_rst u_srio_clk_rst (
213 .sys_clkp(srio_refclk_p),
214 .sys_clkn(srio_refclk_n),
215 .sys_rst(!k7_rstn),
216 .p0_port_initialized(p0_port_initialized),
217 .p0_phy_rcvd_link_reset(p0_phy_rcvd_link_reset),
218 .p0_force_reinit(p0_force_reinit),
219 .p0_mode_1x(p0_mode_1x),
220 .p0_log_clk(p0_log_clk),
221 .p0_phy_clk(p0_phy_clk),
222 .p0_gt_pcs_clk(p0_gt_pcs_clk),
223 .p0_gt_clk(p0_gt_clk),
224 .p0_refclk(p0_refclk),
225 .p0_drpclk(p0_drpclk),
226 .p0_controlled_force_reinit(p0_controlled_force_reinit),
227 .p0_cfg_rst(p0_cfg_rst),
228 .p0_log_rst(p0_log_rst),
229 .p0_buf_rst(p0_buf_rst),
230 .p0_phy_rst(p0_phy_rst),
231 .p0_gt_pcs_rst(p0_gt_pcs_rst),
232 .p0_clk_lock(p0_clk_lock),
233 .p1_port_initialized(p1_port_initialized),
234 .p1_phy_rcvd_link_reset(p1_phy_rcvd_link_reset),
235 .p1_force_reinit(p1_force_reinit),
236 .p1_mode_1x(p1_mode_1x),
237 .p1_log_clk(p1_log_clk),
238 .p1_phy_clk(p1_phy_clk),
239 .p1_gt_pcs_clk(p1_gt_pcs_clk),
240 .p1_gt_clk(p1_gt_clk),
241 .p1_refclk(p1_refclk),
242 .p1_drpclk(p1_drpclk),
243 .p1_controlled_force_reinit(p1_controlled_force_reinit),
244 .p1_cfg_rst(p1_cfg_rst),
245 .p1_log_rst(p1_log_rst),
246 .p1_buf_rst(p1_buf_rst),
247 .p1_phy_rst(p1_phy_rst),
248 .p1_gt_pcs_rst(p1_gt_pcs_rst),
249 .p1_clk_lock(p1_clk_lock)
250 );
251
252 p0_srio_dut_2x u_p0_srio_dut_2x (
253 .log_clk(p0_log_clk),
254 .phy_clk(p0_phy_clk),
255 .gt_pcs_clk(p0_gt_pcs_clk),
256 .gt_clk(p0_gt_clk),
257 .refclk(p0_refclk),
258 .drpclk(p0_drpclk),
259 .controlled_force_reinit(p0_controlled_force_reinit),
260 .cfg_rst(p0_cfg_rst),
261 .log_rst(p0_log_rst),
262 .buf_rst(p0_buf_rst),
263 .phy_rst(p0_phy_rst),
264 .gt_pcs_rst(p0_gt_pcs_rst),
265 .maintr_rst(p0_maintr_rst),
266 .clk_lock(p0_clk_lock),
267 .srio_rxn0(p0_srio_rxn0),
268 .srio_rxp0(p0_srio_rxp0),
269 .srio_rxn1(p0_srio_rxn1),
270 .srio_rxp1(p0_srio_rxp1),
271 .srio_txn0(p0_srio_txn0),
272 .srio_txp0(p0_srio_txp0),
273 .srio_txn1(p0_srio_txn1),
274 .srio_txp1(p0_srio_txp1),
275 .iotx_tvalid(p0_iotx_tvalid),
276 .iotx_tready(p0_iotx_tready),
277 .iotx_tlast(p0_iotx_tlast),
278 .iotx_tdata(p0_iotx_tdata),
279 .iotx_tkeep(p0_iotx_tkeep),
280 .iotx_tuser(p0_iotx_tuser),
281 .iorx_tvalid(p0_iorx_tvalid),
282 .iorx_tready(p0_iorx_tready),
283 .iorx_tlast(p0_iorx_tlast),
284 .iorx_tdata(p0_iorx_tdata),
285 .iorx_tkeep(p0_iorx_tkeep),
286 .iorx_tuser(p0_iorx_tuser),
287 .usrtx_tvalid(p0_usrtx_tvalid),
288 .usrtx_tready(p0_usrtx_tready),
289 .usrtx_tlast(p0_usrtx_tlast),
290 .usrtx_tdata(p0_usrtx_tdata),
291 .usrtx_tkeep(p0_usrtx_tkeep),
292 .usrtx_tuser(p0_usrtx_tuser),
293 .usrrx_tvalid(p0_usrrx_tvalid),
294 .usrrx_tready(p0_usrrx_tready),
295 .usrrx_tlast(p0_usrrx_tlast),
296 .usrrx_tdata(p0_usrrx_tdata),
297 .usrrx_tkeep(p0_usrrx_tkeep),
298 .usrrx_tuser(p0_usrrx_tuser),
299 .maintr_awvalid(p0_maintr_awvalid),
300 .maintr_awready(p0_maintr_awready),
301 .maintr_awaddr(p0_maintr_awaddr),
302 .maintr_wvalid(p0_maintr_wvalid),
303 .maintr_wready(p0_maintr_wready),
304 .maintr_wdata(p0_maintr_wdata),
305 .maintr_bvalid(p0_maintr_bvalid),
306 .maintr_bready(p0_maintr_bready),
307 .maintr_bresp(p0_maintr_bresp),
308 .maintr_arvalid(p0_maintr_arvalid),
309 .maintr_arready(p0_maintr_arready),
310 .maintr_araddr(p0_maintr_araddr),
311 .maintr_rvalid(p0_maintr_rvalid),
312 .maintr_rready(p0_maintr_rready),
313 .maintr_rdata(p0_maintr_rdata),
314 .maintr_rresp(p0_maintr_rresp),
315 .sim_train_en(p0_sim_train_en),
316 .phy_mce(p0_phy_mce),
317 .phy_link_reset(p0_phy_link_reset),
318 .force_reinit(p0_force_reinit),
319 .port_initialized(p0_port_initialized),
320 .link_initialized(p0_link_initialized),
321 .idle_selected(p0_idle_selected),
322 .idle2_selected(p0_idle2_selected),
323 .phy_rcvd_mce(p0_phy_rcvd_mce),
324 .phy_rcvd_link_reset(p0_phy_rcvd_link_reset),
325 .port_error(p0_port_error),
326 .mode_1x(p0_mode_1x),
327 .port_timeout(p0_port_timeout),
328 .srio_host(p0_srio_host),
329 .phy_debug(p0_phy_debug),
330 .gtrx_disperr_or(p0_gtrx_disperr_or),
331 .gtrx_notintable_or(p0_gtrx_notintable_or),
332 .deviceid(p0_deviceid),
333 .port_decode_error(p0_port_decode_error),
334 .p1_gt0_qplloutclk_i(p1_gt0_qplloutclk_i),
335 .p1_gt0_qplloutrefclk_i(p1_gt0_qplloutrefclk_i)
336 );
337
338
339 p1_srio_dut_2x u_p1_srio_dut_2x (
340 .log_clk(p1_log_clk),
341 .phy_clk(p1_phy_clk),
342 .gt_pcs_clk(p1_gt_pcs_clk),
343 .gt_clk(p1_gt_clk),
344 .refclk(p1_refclk),
345 .drpclk(p1_drpclk),
346 .controlled_force_reinit(p1_controlled_force_reinit),
347 .cfg_rst(p1_cfg_rst),
348 .log_rst(p1_log_rst),
349 .buf_rst(p1_buf_rst),
350 .phy_rst(p1_phy_rst),
351 .gt_pcs_rst(p1_gt_pcs_rst),
352 .maintr_rst(p1_maintr_rst),
353 .clk_lock(p1_clk_lock),
354 .srio_rxn0(p1_srio_rxn0),
355 .srio_rxp0(p1_srio_rxp0),
356 .srio_rxn1(p1_srio_rxn1),
357 .srio_rxp1(p1_srio_rxp1),
358 .srio_txn0(p1_srio_txn0),
359 .srio_txp0(p1_srio_txp0),
360 .srio_txn1(p1_srio_txn1),
361 .srio_txp1(p1_srio_txp1),
362 .iotx_tvalid(p1_iotx_tvalid),
363 .iotx_tready(p1_iotx_tready),
364 .iotx_tlast(p1_iotx_tlast),
365 .iotx_tdata(p1_iotx_tdata),
366 .iotx_tkeep(p1_iotx_tkeep),
367 .iotx_tuser(p1_iotx_tuser),
368 .iorx_tvalid(p1_iorx_tvalid),
369 .iorx_tready(p1_iorx_tready),
370 .iorx_tlast(p1_iorx_tlast),
371 .iorx_tdata(p1_iorx_tdata),
372 .iorx_tkeep(p1_iorx_tkeep),
373 .iorx_tuser(p1_iorx_tuser),
374 .usrtx_tvalid(p1_usrtx_tvalid),
375 .usrtx_tready(p1_usrtx_tready),
376 .usrtx_tlast(p1_usrtx_tlast),
377 .usrtx_tdata(p1_usrtx_tdata),
378 .usrtx_tkeep(p1_usrtx_tkeep),
379 .usrtx_tuser(p1_usrtx_tuser),
380 .usrrx_tvalid(p1_usrrx_tvalid),
381 .usrrx_tready(p1_usrrx_tready),
382 .usrrx_tlast(p1_usrrx_tlast),
383 .usrrx_tdata(p1_usrrx_tdata),
384 .usrrx_tkeep(p1_usrrx_tkeep),
385 .usrrx_tuser(p1_usrrx_tuser),
386 .maintr_awvalid(p1_maintr_awvalid),
387 .maintr_awready(p1_maintr_awready),
388 .maintr_awaddr(p1_maintr_awaddr),
389 .maintr_wvalid(p1_maintr_wvalid),
390 .maintr_wready(p1_maintr_wready),
391 .maintr_wdata(p1_maintr_wdata),
392 .maintr_bvalid(p1_maintr_bvalid),
393 .maintr_bready(p1_maintr_bready),
394 .maintr_bresp(p1_maintr_bresp),
395 .maintr_arvalid(p1_maintr_arvalid),
396 .maintr_arready(p1_maintr_arready),
397 .maintr_araddr(p1_maintr_araddr),
398 .maintr_rvalid(p1_maintr_rvalid),
399 .maintr_rready(p1_maintr_rready),
400 .maintr_rdata(p1_maintr_rdata),
401 .maintr_rresp(p1_maintr_rresp),
402 .sim_train_en(p1_sim_train_en),
403 .phy_mce(p1_phy_mce),
404 .phy_link_reset(p1_phy_link_reset),
405 .force_reinit(p1_force_reinit),
406 .port_initialized(p1_port_initialized),
407 .link_initialized(p1_link_initialized),
408 .idle_selected(p1_idle_selected),
409 .idle2_selected(p1_idle2_selected),
410 .phy_rcvd_mce(p1_phy_rcvd_mce),
411 .phy_rcvd_link_reset(p1_phy_rcvd_link_reset),
412 .port_error(p1_port_error),
413 .mode_1x(p1_mode_1x),
414 .port_timeout(p1_port_timeout),
415 .srio_host(p1_srio_host),
416 .phy_debug(p1_phy_debug),
417 .gtrx_disperr_or(p1_gtrx_disperr_or),
418 .gtrx_notintable_or(p1_gtrx_notintable_or),
419 .deviceid(p1_deviceid),
420 .port_decode_error(p1_port_decode_error),
421 .p1_gt0_qplloutclk_i(p1_gt0_qplloutclk_i),
422 .p1_gt0_qplloutrefclk_i(p1_gt0_qplloutrefclk_i)
423 );
424 /*srio_dut srio_dut_inst
425 (.sys_clkp (srio_refclk_p),
426 .sys_clkn (srio_refclk_n),
427 .log_clk (log_clk),
428 .phy_clk (phy_clk),
429 .gt_pcs_clk (gt_pcs_clk),
430
431 .sys_rst (!k7_rstn),
432 .log_rst (log_rst),
433 .phy_rst (phy_rst),
434 .clk_lock (clk_lock),
435
436 .srio_rxn0 (srio_rxn0),
437 .srio_rxp0 (srio_rxp0),
438 .srio_rxn1 (srio_rxn1),
439 .srio_rxp1 (srio_rxp1),
440 .srio_rxn2 (srio_rxn2),
441 .srio_rxp2 (srio_rxp2),
442 .srio_rxn3 (srio_rxn3),
443 .srio_rxp3 (srio_rxp3),
444
445 .srio_txn0 (srio_txn0),
446 .srio_txp0 (srio_txp0),
447 .srio_txn1 (srio_txn1),
448 .srio_txp1 (srio_txp1),
449 .srio_txn2 (srio_txn2),
450 .srio_txp2 (srio_txp2),
451 .srio_txn3 (srio_txn3),
452 .srio_txp3 (srio_txp3),
453
454 .iotx_tvalid (iotx_tvalid),
455 .iotx_tready (iotx_tready),
456 .iotx_tlast (iotx_tlast),
457 .iotx_tdata (iotx_tdata),
458 .iotx_tkeep (iotx_tkeep),
459 .iotx_tuser (iotx_tuser),
460
461 .iorx_tvalid (iorx_tvalid),
462 .iorx_tready (iorx_tready),
463 .iorx_tlast (iorx_tlast),
464 .iorx_tdata (iorx_tdata),
465 .iorx_tkeep (iorx_tkeep),
466 .iorx_tuser (iorx_tuser),
467
468 .maintr_rst (maintr_rst),
469
470 .maintr_awvalid (maintr_awvalid),
471 .maintr_awready (maintr_awready),
472 .maintr_awaddr (maintr_awaddr),
473 .maintr_wvalid (maintr_wvalid),
474 .maintr_wready (maintr_wready),
475 .maintr_wdata (maintr_wdata),
476 .maintr_bvalid (maintr_bvalid),
477 .maintr_bready (maintr_bready),
478 .maintr_bresp (maintr_bresp),
479
480 .maintr_arvalid (maintr_arvalid),
481 .maintr_arready (maintr_arready),
482 .maintr_araddr (maintr_araddr),
483 .maintr_rvalid (maintr_rvalid),
484 .maintr_rready (maintr_rready),
485 .maintr_rdata (maintr_rdata),
486 .maintr_rresp (maintr_rresp),
487
488 .sim_train_en (sim_train_en),
489 .phy_mce (phy_mce),
490 .phy_link_reset (phy_link_reset),
491 .force_reinit (force_reinit),
492
493 .port_initialized (port_initialized),
494 .link_initialized (link_initialized),
495 .idle_selected (idle_selected),
496 .idle2_selected (idle2_selected),
497 .phy_rcvd_mce (phy_rcvd_mce),
498 .phy_rcvd_link_reset (phy_rcvd_link_reset),
499 .port_error (port_error),
500 .mode_1x (mode_1x),
501 .port_timeout (port_timeout),
502 .srio_host (srio_host),
503 .phy_debug (phy_debug),
504 .gtrx_disperr_or (gtrx_disperr_or),
505 .gtrx_notintable_or (gtrx_notintable_or),
506
507 .deviceid (deviceid),
508 .port_decode_error (port_decode_error),
509 .CONTROL (CONTROL2)
510 );*/
511
512 srio_user #
513 (
514 .DSP_ADD(34'h108F0000)
515 )
516 u_p0_srio_user (
517 .log_clk(p0_log_clk),
518 .log_rst(p0_log_rst),
519 .port_initialized(p0_port_initialized),
520 .iorx_tvalid(p0_iorx_tvalid),
521 .iorx_tready(p0_iorx_tready),
522 .iorx_tlast(p0_iorx_tlast),
523 .iorx_tdata(p0_iorx_tdata),
524 .iorx_tkeep(p0_iorx_tkeep),
525 .iorx_tuser(p0_iorx_tuser),
526 .iotx_tvalid(p0_iotx_tvalid),
527 .iotx_tready(p0_iotx_tready),
528 .iotx_tlast(p0_iotx_tlast),
529 .iotx_tdata(p0_iotx_tdata),
530 .iotx_tkeep(p0_iotx_tkeep),
531 .iotx_tuser(p0_iotx_tuser)
532 );
533
534 srio_user #
535 (
536 .DSP_ADD(34'h118F0000)
537 )
538 u_p1_srio_user (
539 .log_clk(p1_log_clk),
540 .log_rst(p1_log_rst),
541 .port_initialized(p1_port_initialized),
542 .iorx_tvalid(p1_iorx_tvalid),
543 .iorx_tready(p1_iorx_tready),
544 .iorx_tlast(p1_iorx_tlast),
545 .iorx_tdata(p1_iorx_tdata),
546 .iorx_tkeep(p1_iorx_tkeep),
547 .iorx_tuser(p1_iorx_tuser),
548 .iotx_tvalid(p1_iotx_tvalid),
549 .iotx_tready(p1_iotx_tready),
550 .iotx_tlast(p1_iotx_tlast),
551 .iotx_tdata(p1_iotx_tdata),
552 .iotx_tkeep(p1_iotx_tkeep),
553 .iotx_tuser(p1_iotx_tuser)
554 );
555
556
557 chipscope_icon u_icon (
558 .CONTROL0(CONTROL0), // INOUT BUS [35:0]
559 .CONTROL1(CONTROL1), // INOUT BUS [35:0]
560 .CONTROL2(CONTROL2),
561 .CONTROL3(CONTROL3)
562 );
563
564 chipscope_ila u0_ila (
565 .CONTROL(CONTROL0), // INOUT BUS [35:0]
566 .CLK(p0_log_clk), // IN
567 .TRIG0(
568 {
569 p0_port_decode_error,
570 p0_iorx_tready,
571 p0_iorx_tval,
572 full,
573 empty,
574 fifo_prog_full,
575 p0_iorx_tdata,
576 fifo_dout_v,
577 fifo_rden,
578 state_cnt,
579 state,
580 p0_clk_lock,
581 p0_iotx_tdata,
582 p0_iotx_tkeep,
583 p0_iotx_tuser,
584 p0_iotx_tvalid,
585 p0_iotx_tready,
586 p0_iotx_tlast
587 }
588 ) // IN BUS [255:0]
589 );
590
591
592
593 chipscope_ila u1_ila (
594 .CONTROL(CONTROL1), // INOUT BUS [35:0]
595 .CLK(p0_log_clk), // IN
596 .TRIG0(
597 {
598 p0_deviceid,
599 p0_iorx_tdata,
600 p0_iorx_tkeep,
601 p0_iorx_tuser,
602 p0_iorx_tvalid,
603 p0_iorx_tready,
604 p0_iorx_tlast,
605 p0_port_initialized,
606 p0_link_initialized,
607 p0_mode_1x,
608 p0_phy_rcvd_link_reset
609 }
610 ) // IN BUS [255:0]
611 );
612
613
614 chipscope_ila u2_ila (
615 .CONTROL(CONTROL2), // INOUT BUS [35:0]
616 .CLK(p1_log_clk), // IN
617 .TRIG0(
618 {
619 p1_port_decode_error,
620 p1_iorx_tready,
621 p1_iorx_tval,
622 full,
623 empty,
624 fifo_prog_full,
625 p1_iorx_tdata,
626 fifo_dout_v,
627 fifo_rden,
628 state_cnt,
629 state,
630 p1_clk_lock,
631 p1_iotx_tdata,
632 p1_iotx_tkeep,
633 p1_iotx_tuser,
634 p1_iotx_tvalid,
635 p1_iotx_tready,
636 p1_iotx_tlast
637 }
638 ) // IN BUS [255:0]
639 );
640
641
642
643 chipscope_ila u3_ila (
644 .CONTROL(CONTROL3), // INOUT BUS [35:0]
645 .CLK(p1_log_clk), // IN
646 .TRIG0(
647 {
648 p1_deviceid,
649 p1_iorx_tdata,
650 p1_iorx_tkeep,
651 p1_iorx_tuser,
652 p1_iorx_tvalid,
653 p1_iorx_tready,
654 p1_iorx_tlast,
655 p1_port_initialized,
656 p1_link_initialized,
657 p1_mode_1x,
658 p1_phy_rcvd_link_reset
659 }
660 ) // IN BUS [255:0]
661 );
662 endmodule
