xilinx的serdes接收时钟坑
ilinx的7 series fpga transceivers wizard用于自定义的serdes编码。
要选择多个serdes端口，如下图，点击对应的名称，然后右边选择use该设备就可以。
生成后example文件中的support GT_USRCLK_SOURCE 文件，有个时钟文件。打开了悲剧了。所以经常debug调试，用其他的接收的时钟，无缘无故的出现no arm clk。实在是火大。
module k7_serdesx8_GT_USRCLK_SOURCE 这个文件
BUFG txoutclk_bufg0_i
(
.I (gt0_txoutclk_i),
.O (gt0_txusrclk_i)
);
BUFG rxoutclk_bufg1_i
(
.I (gt0_rxoutclk_i),
.O (gt0_rxusrclk_i)
);
assign GT0_TXUSRCLK_OUT = gt0_txusrclk_i;
assign GT0_TXUSRCLK2_OUT = gt0_txusrclk_i;
assign GT0_RXUSRCLK_OUT = gt0_rxusrclk_i;
assign GT0_RXUSRCLK2_OUT = gt0_rxusrclk_i;
assign GT1_TXUSRCLK_OUT = gt0_txusrclk_i;
assign GT1_TXUSRCLK2_OUT = gt0_txusrclk_i;
assign GT1_RXUSRCLK_OUT = gt0_rxusrclk_i;
assign GT1_RXUSRCLK2_OUT = gt0_rxusrclk_i;
assign GT2_TXUSRCLK_OUT = gt0_txusrclk_i;
assign GT2_TXUSRCLK2_OUT = gt0_txusrclk_i;
assign GT2_RXUSRCLK_OUT = gt0_rxusrclk_i;
assign GT2_RXUSRCLK2_OUT = gt0_rxusrclk_i;
assign GT3_TXUSRCLK_OUT = gt0_txusrclk_i;
assign GT3_TXUSRCLK2_OUT = gt0_txusrclk_i;
assign GT3_RXUSRCLK_OUT = gt0_rxusrclk_i;
assign GT3_RXUSRCLK2_OUT = gt0_rxusrclk_i;
办法就是自己增加代码，使用bufg模式，引出其他的时钟。代码如下：
BUFG txoutclk_bufg0_i
(
.I (gt0_txoutclk_i),
.O (gt0_txusrclk_i)
);
BUFG rxoutclk_bufg0_i
(
.I (gt0_rxoutclk_i),
.O (gt0_rxusrclk_i)
);
////////////////////////////////1
BUFG txoutclk_bufg1_i
(
.I (gt1_txoutclk_i),
.O (gt1_txusrclk_i)
);
BUFG rxoutclk_bufg1_i
(
.I (gt1_rxoutclk_i),
.O (gt1_rxusrclk_i)
);
////////////////////////////////2
BUFG txoutclk_bufg2_i
(
.I (gt2_txoutclk_i),
.O (gt2_txusrclk_i)
);
BUFG rxoutclk_bufg2_i
(
.I (gt2_rxoutclk_i),
.O (gt2_rxusrclk_i)
);
////////////////////////////////3
BUFG txoutclk_bufg3_i
(
.I (gt3_txoutclk_i),
.O (gt3_txusrclk_i)
);
BUFG rxoutclk_bufg3_i
(
.I (gt3_rxoutclk_i),
.O (gt3_rxusrclk_i)
);
assign GT0_TXUSRCLK_OUT = gt0_txusrclk_i;
assign GT0_TXUSRCLK2_OUT = gt0_txusrclk_i;
assign GT0_RXUSRCLK_OUT = gt0_rxusrclk_i;
assign GT0_RXUSRCLK2_OUT = gt0_rxusrclk_i;
assign GT1_TXUSRCLK_OUT = gt1_txusrclk_i;
assign GT1_TXUSRCLK2_OUT = gt1_txusrclk_i;
assign GT1_RXUSRCLK_OUT = gt1_rxusrclk_i;
assign GT1_RXUSRCLK2_OUT = gt1_rxusrclk_i;
assign GT2_TXUSRCLK_OUT = gt2_txusrclk_i;
assign GT2_TXUSRCLK2_OUT = gt2_txusrclk_i;
assign GT2_RXUSRCLK_OUT = gt2_rxusrclk_i;
assign GT2_RXUSRCLK2_OUT = gt2_rxusrclk_i;
assign GT3_TXUSRCLK_OUT = gt3_txusrclk_i;
assign GT3_TXUSRCLK2_OUT = gt3_txusrclk_i;
assign GT3_RXUSRCLK_OUT = gt3_rxusrclk_i;
assign GT3_RXUSRCLK2_OUT = gt3_rxusrclk_i;
这样每个端口发送和接收的时钟都是独立的。如果不是这么设定，那个可能多个端口接收时钟不一样就完蛋
