VHDL中并置运算符的注意点

并置运算符的条件是 操作数是支持逻辑运算的任何数据类型.

而支持逻辑运算的数据类型是:BIT, BIT_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, STD_LOGIC_VECTOR 这些类型.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
----------------------------
ENTITY TESTMU IS
PORT (
Z: OUT STD_LOGIC_VECTOR(0 TO 7)
);
END ENTITY;
----------------------------
ARCHITECTURE EXAMPLE OF TESTMU IS
SIGNAL X: BIT;

BEGIN
X <= '1';
Z <= X & "1000000";
END EXAMPLE; 

这种情况编译报错,虽然提示是:
Error (10327): VHDL error at testmu.vhd(15): can't determine definition of operator ""&"" -- found 0 possible definitions
说是 & 没有定义,但是实质是虽然位数是匹配的,但是两种数据类型不匹配.

Z是STD_LOGIC_VECTOR类型,而X是BIT类型.所以更改方法是:

要么把Z改成 BIT_VECTOR类型, 或者把X 改成 STD_LOGIC类型,就没有问题了.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
----------------------------
ENTITY TESTMU IS
PORT (
Z: OUT STD_LOGIC_VECTOR(0 TO 7)
);
END ENTITY;
----------------------------
ARCHITECTURE EXAMPLE OF TESTMU IS
SIGNAL X: STD_LOGIC;

BEGIN
X <= '1';
Z <= X & "1000000";
END EXAMPLE;