read IEEE std for verolog(2)

read IEE standard for verilog (2)

1、阅读前言

前面大致地看完了序言，了解了一下verilog的起源以及基本特性。接下来往下读有相关链接和目录，然后是正文。今天暂时阅读目录，有时间再的话看一下第一章。

2、阅读内容

目录的第一章是总说，余下的是细节。只要阅读第一章，就可以大致地了解文章的结构。

1.1 Scope
Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first
revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the
1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE
Std 1800™-2005.

这是一个概述，大致描述了这个文章的定位。

1.2 Conventions used in this standard
This standard is organized into clauses, each of which focuses on a specific area of the language. There are
subclauses within each clause to discuss individual constructs and concepts. The discussion begins with an
introduction and an optional rationale for the construct or the concept, followed by syntax and semantic
descriptions, followed by some examples and notes.

这里声明了一些约定，用于理解文章。

子文章的结构是先概念，再语法，最后例子的模式。

1.3 Syntactic description
The formal syntax of the Verilog HDL is described using Backus-Naur Form (BNF). The following
conventions are used:

语句规范：

— Lowercase words, some containing embedded underscores, are used to denote syntactic categories.
For example:
module_declaration
— Boldface words are used to denote reserved keywords, operators, and punctuation marks as a
required part of the syntax. For example:
module => ;
— A vertical bar separates alternative items unless it appears in boldface, in which case it stands for
itself. For example:
unary_operator ::=
+ | - | ! | ~ | & | ~& | | | ~| | ^ | ~^ | ^~
— Square brackets enclose optional items. For example:
input_declaration ::= input [range] list_of_variables ;
— Braces ({}) enclose a repeated item unless it appears in boldface, in which case it stands for itself.
The item may appear zero or more times; the repetitions occur from left to right as with an
equivalent left-recursive rule. Thus, the following two rules are equivalent:
list_of_param_assignments ::= param_assignment { , param_assignment }
list_of_param_assignments ::=
param_assignment
| list_of_param_assignment , param_assignment
— If the name of any category starts with an italicized part, it is equivalent to the category name
without the italicized part. The italicized part is intended to convey some semantic information. For
example, “msb_index” and “lsb_index” are equivalent to “index.”

第一条是小写字作为语句范畴（包括下划线），第二条是黑体字的作用。其他的几项就不细看了，这是verilog编译器开发人员需要看的。

1.4 Use of color in this standard
This standard uses a minimal amount of color to enhance readability. The coloring is not essential and does
not affect the accuracy of this standard when viewed in pure black and white. Color is used to show cross
references that are hyperlinked to other portions of this standard. These hyperlinked cross references are
shown in underlined-blue text (hyperlinking works when this standard is viewed interactively as a PDF file).

verilog中颜色的使用，只是为了提高可读性，不具备必要性。

1.5 Contents of this standard
A synopsis of the clauses and annexes is presented as a quick reference. There are 28 clauses and 9 annexes.
All clauses, as well as Annex A, Annex B, and Annex G, are normative parts of this standard. Annex C,
Annex D, Annex H, and Annex I are included for informative purposes only.

这部分介绍了条款和附件的作用以及位置。

目录的第二节显示了一些相关的参考文件。

3、阅读结果

目前阅读到第3章-Lexical conventions（词法约定）。