UVM——virtual sequencer和virtual sequence

 

 0. 介绍

　　整理UVM中的virtual sequence和virtual sequencer。

 

1. virtual sequencer

 

特点

1. high-level control of multiple sequencers。在virtual sequencer中包含driver sequencer和virtual sequencer的句柄。

2. Virtual sequencer that is not attached to a driver 。它不与driver进行item传输，所以不需要建立端口连接。

3. does not process items。所以virtual sequencer定义的时候没有类型参数。

 

 

// 这是UVM UG中给的例子
class simple_virtual_sequencer extends uvm_sequencer;
    eth_sequencer eth_seqr;
    cpu_sequencer cpu_seqr;
// Constructor
function new(input string name="simple_virtual_sequencer",
    input uvm_component parent=null);
    super.new(name, parent);
endfunction
// UVM automation macros for sequencers
`uvm_component_utils(simple_virtual_sequencer)
endclass: simple_virtual_sequencer

 

从上面的例子中可以看出，在virtual sequencer中只定义sequencer句柄，并不会实例化（申请内存空间）它们，会通过指针传递将一些实例化之后的真正的sequencer的句柄传进来，一般是在connect phase，如下：

v_sequencer.cpu_seqr = cpu_seqr;
v_sequencer.eth_seqr = eth_seqr;

 

2. virtual sequence

 

当验证平台中有多个组件需要并行产生激励，为了控制组建件激励同步，可以用virtual sequence。

 

特点

1. 与一个virtual sequencer绑定。

2. 在其中可以定义sequence和virtual sequence，并在其中启动sequence，这些sequence启动的sequencer通过virtual sequencer传递进来。

3. 不产生item，定义的时候不需要类型参数。

 

// UVM UG中的virtual sequence的实例
class simple_virt_seq extends uvm_sequence;
    `uvm_declare_p_sequencer(vsequencer) //自己加的
... // Constructor and UVM automation macros
    // A sequence from the cpu sequencer library
    cpu_config_seq conf_seq;
    // A sequence from the ethernet subsequencer library
    eth_large_payload_seq frame_seq;
    // A virtual sequence from this sequencer's library
    random_traffic_virt_seq rand_virt_seq;
    virtual task body();
    // Invoke a sequence in the cpu subsequencer.
        `uvm_do_on(conf_seq, p_sequencer.cpu_seqr)
    // Invoke a sequence in the ethernet subsequencer.
        `uvm_do_on(frame_seq, p_sequencer.eth_seqr)
    // Invoke another virtual sequence in this sequencer.
        `uvm_do(rand_virt_seq)
    endtask : body
endclass : simple_virt_seq

p_sequencer就是启动这个virtual sequence的virtual sequencer。

 

virtual sequence和嵌套sequence的一个区别是，嵌套sequence中的sequence都在同一个sequencer上启动（通过sequencer仲裁决定）；而在virtual sequence中的sequence可以在不同sequencer实体上同时启动。

 

3. 参考例子

 

下面例子中，向virtual sequencer中传递sequencer句柄的方式有两种，一种直接通过层次化引用传递；另一种通过config_db机制。

 

class simple_tb extends uvm_env;
    cpu_env_c cpu0; // Reuse a cpu verification component.
    eth_env_c eth0; // Reuse an ethernet verification component.
    simple_virtual_sequencer v_sequencer;
    ... // Constructor and UVM automation macros
    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        // Configuration: Set the default sequence for the virtual sequencer.
        uvm_config_db#(uvm_object_wrapper)::set(this,
        "v_sequencer.run_phase",
        "default_sequence",
        simple_virt_seq.type_id::get());
        // Build envs with subsequencers.
        cpu0 = cpu_env_c::type_id::create("cpu0", this);
        eth0 = eth_env_c::type_id::create("eth0", this);
        // Build the virtual sequencer.
        v_sequencer =
        simple_virtual_sequencer::type_id::create("v_sequencer",this);
    endfunction : build_phase
    // Connect virtual sequencer to subsequencers.
    function void connect();
        v_sequencer.cpu_seqr = cpu0.master[0].sequencer; // 直接通过指针传递实例化的driver sequencer
        uvm_config_db#(uvm_sequencer)::set(this,”v_sequencer”,
        ”eth_seqr”,eth0.tx_rx_agent.sequencer);// 通过config_db机制传递实例化的driver sequencer
    endfunction : connect
endclass: simple_tb