vivado 编译vcs

https://zhuanlan.zhihu.com/p/38623543

使用VCS+Verdi对Xilinx IP仿真

 

 https://blog.csdn.net/shawge/article/details/107582479

如何使用Synopsys VCS在Vivado中编译库并执行仿真

 

 

https://support.xilinx.com/s/article/60153?language=en_US

 

SOLUTION

The problem could be related to the read/write permissions of the tools/user.

synopsys_sim.setup is a file from the Synopsys installation in which all of the Default Simulation env variables and parameters are defined. 

During the compilation task, Vivado makes a copy of this file at the beginning of the process and adds the compiled libraries at the bottom of the file (library mapping). 

 
Once the files is created/copied in the working directory for compilation, the Vivado compilation tool starts to write to the directory where the libraries have been compiled.

If this file is not present or can not be created, then the process fails with the error message above.
 

A work-around is to copy the "Synopsys_sim.setup" file from the Synopsis installation to the working directory and the tool will append the library mappings.

 

verilog仿真中几种生成fsdb波形的方式

 

 

https://zhuanlan.zhihu.com/p/259543794

 

• vcs编译需要添加-debug_access选项

$ vcs tb.v -debug_access

• 编写用于存放ucli命令的文件.ucli.cmd，文件名随意

fsdbDumpvars 0 tb
run

• 执行仿真指定参数

$ ./simv  -ucli -i .ucli.cmd