XIAO张万里

摘要： 使用环境：Quartus II 8.0 + DE2(Cyclone II EP2C35F627C6) 1 占空比为50%的6分频电路。 源代码： module clk_mod6_divide( //input clk, rst_n, //output clk_divide, ); input clk; input rst_n; output clk_divide; reg... 阅读全文

摘要： 将WM8731配置成从模式（主时钟为18.432MHz，采样率为48KHz），数字音频接口的时序由FPGA产生。 AUD_XCK是WM8731的系统时钟为18432000Hz,18432000=384*48000(为采样频率fs).即系统时钟是384倍的过采样率。 AUD_BCLK数字音频位时钟，AUD_BCLK=48000×16（量化位数bits）×2（双声道）= 1536000。另外AUD... 阅读全文

摘要： My Favorite Trip Someone once said: "you can either travel or read, and either your body or soul must be on the way." I like it which gives me strength to challenge myself. One of my favorite trips is been Tibet. On last winter holiday, I visited my uncle who lives and makes business in Ti 阅读全文