uvm_reg_backdoor——寄存器模型（十）

寄存器有前门和后门两种访问方式，这儿只看后门访问方式

 

//------------------------------------------------------------------------------
// Class: uvm_reg_backdoor
//
// Base class for user-defined back-door register and memory access.
//
// This class can be extended by users to provide user-specific back-door access
// to registers and memories that are not implemented in pure SystemVerilog
// or that are not accessible using the default DPI backdoor mechanism.
//------------------------------------------------------------------------------

class uvm_reg_backdoor extends uvm_object;

   // Function: new
   //
   // Create an instance of this class
   //
   // Create an instance of the user-defined backdoor class
   // for the specified register or memory
   //
   function new(string name = "");
      super.new(name);
   endfunction: new