06 2021 档案

常用FPGA功能块记录
摘要：//runing flag led reg[23:0]led_count = 24'd0; always @ (posedge clk_25m or negedge rst_n) begin if(~rst_n)begin led_count <= 24'd0; led <= 1'b0; end e 阅读全文
posted @ 2021-06-19 15:53 昊天一怪 阅读(79) 评论(0) 推荐(0) 编辑