每天一个vim小技巧[4] - 导入模板

vim 导入文件并且打印到当前文件中的命令是

:r <file>

我们可以把模板提前放到 home 目录下，并通过这个命令导入

比如，可以把 testbench 读写文件的内容放到 ~/.vhdl/.f

use ieee.std_logic_textio.all;
use std.textio.all;
use ieee.numeric_std.all;

file fin_hd: text open read_mode is
    "";
file fout_hd: text open write_mode is
    "";

constant CLK_PERIOD : time:= 10 ns;

signal clk : std_logic:='0';
signal rst : std_logic:='0';

fin_proc : process(clk, rst)
variable v_line  : line;
variable v_en    : std_logic;
variable v_din   : integer;
begin
    if(rst='1') then
        en    <=  '0';
        din   <=  (others=>'0');
    else
        if(clk'event and clk='1') then
            if(not endfile(fin_hd)) then
                readline(fin_hd,v_line);
                read(v_line,v_en);
                read(v_line,v_din);
                en      <=  v_en;
                din     <=  std_logic_vector(to_signed(v_din,12));
            else
                en    <=  '0';
                din   <=  (others=>'0');
            end if;
        end if;
    end if;
end process;

fout_proc : process(clk,rst)
variable v_line: line;
-- variable v_vld   : std_logic;
variable v_dout  : integer;
begin
    if(rst='1') then
    else
        if(clk'event and clk='1') then
            if(vld='1') then
                v_dout:= to_integer(signed(dout));
                write(v_line,v_dout);
--                 write(v_line,HT);
                writeline(fout_hd,v_line);
            end if;
        end if;
    end if;
end process;

clk_proc : process
begin
    wait for CLK_PERIOD/2;
    clk <= not clk;
end process;

rst <= '1' after CLK_PERIOD*0.5,
       '0' after CLK_PERIOD*20.5;

通过 :r ~/.vhdl/.f 即可导入读写文件的 code