摘要：
保存linux下当前目录下所有文件的相对路径 阅读全文
摘要：
手册中的基本命令： CONFIGURE TOOLING Configure user information for all local repositories Sets the name you want attached to your commit transactions Sets the 阅读全文
摘要：
记录使用讯飞SDK创建语音听写Demo的基本流程 阅读全文
摘要：
20170906录一下 内容后续补充 阅读全文
摘要：
Inferring Multipliers and DSP Functions Inferring Multipliers module unsigned_mult (out, a, b); output [15:0] out; input [7:0] a; input [7:0] b; assig 阅读全文
摘要：
Recommended HDL Coding Styles HDL coding styles can have a significant effect on the quality of results that you achieve for programmable logic design 阅读全文
摘要：
Use Clock and Register-Control Architectural Features FPGAs provide device-wide clocks and register control signals that can improve performance. Use 阅读全文
摘要：
Optimizing Physical Implementation and Timing Closure Planning Physical Implementation When planning a design, consider the following elements of phys 阅读全文
摘要：
Optimizing Clocking Schemes Avoid using internally generated clocks (other than PLLs) wherever possible because they can cause functional and timing p 阅读全文
摘要：
主要内容摘自Quartus prime Recommended Design Practices For optimal performance, reliability, and faster time-to-market when designing with Altera devices, y 阅读全文