SHARC 时钟系统

本文解读SHARC 的时钟系统

 

CLKIN:时钟输入。

Pre-divider：前置分频器

Post-divider：后置分频器

 

CCLK：内核时钟

PCLK：外设时钟

 

Register Overview
Power Management Control Register (PMCTL). Governs the operationof the PLL and configures the PLL settings.
Power Management Control Register 1 (PMCTL1). This register controls the various peripheral’s clocks.

时钟控制：可编程的寄存器主要有两个PMCTL和PMCTL1。

 

系统时钟图可以看出，系统时钟由CLKIN 提供，CLKIN有两个去处，一个是通过输入时钟分频器进入到PLL中；

另外一个就是连接到输出时钟发生器中（后置分频器）。前者送入PLL中是为了倍频，后者是使系统运行再Bypass mode（即内核工作在CLKIN上）。

 

CLKIN通过输入时钟分频器，该分频器在使用时钟佳作前置分频器，由PMCTL寄存器的INDIV 位控制，只有一个选项，当INDIV=1，输入时钟被2分频；但INDIV=0，输入时钟未被分频。时钟通过前置分频器后输送给相位侦测器（鉴相器），锁相环中的鉴相器，作用是检测输入信号和输出信号的相位差，并将检测出的相位差信号转换成uD（t）电压信号输出，该信号经低通滤波器滤波后形成压控振荡器的控制电压uC（t），对振荡器输出信号的频率实施控制。

 

时钟系统可编程功能主要有：输入时钟分频器使能，后置分频器使能，系统时钟选择，倍频器系数选择。

 

时钟系统可编程的关键在于：只要会影响到输出时钟发生器的操作，就必须工作在bypass模式。

 

PMCTL1外设时钟使能：每一位对应相应的外设，默认值都为0，置1关闭外设时钟。

 

编程流程：

　　1、先让系统工作在Bypass模式下。（bypass模式，即内核工作在CLKIN时钟下）

　　2、等4096个时钟周期。

　　3、设置前置分频器（INDIV）,设置PLLM、PLLD。

　　4、等4096个时钟周期。

　　5、退出Bypass模式，等待15个周期。

int i, pmctlsetting;

    // Set INDIV bit in PMCTL register
    pmctlsetting = *pPMCTL;
    pmctlsetting |= INDIV;
    *pPMCTL= pmctlsetting;

    // Program PLL multiplier to same value as CLK_CFGx pins/previously programmed value in software厖
    *pPMCTL = pmctlsetting;

    // then place PLL in bypass mode
    pmctlsetting |= PLLBP;
    *pPMCTL = pmctlsetting;

    //Wait for recommended number of cycles
    for (i=0; i<4096; i++)
          NOP;

    // Bring PLL out of bypass mode by clearing PLLBP bit
    *pPMCTL ^= PLLBP;

    for (i=0; i<16; i++)
          NOP;

    pmctlsetting = *pPMCTL;
    // Clear the previous PLL multiplier
    pmctlsetting &= ~PLLM63;
    // Clear the INDIV bit
    pmctlsetting &= ~INDIV;
    // or set the INDIV bit
    // *pMCTL |= INDIV;
    *pPMCTL= pmctlsetting;
    
// CLKIN= 25 MHz, Multiplier= 16, Divisor= 2, CCLK_SDCLK_RATIO 2.5.
// Fcclk = (CLKIN * 2 * M) / (N * D)
// VCO frequency = 2*fINPUT*PLLM = 2*25*16 = 800 <= fVCOmax (800 MHz)
// M = 1 to 64, N = 2,4,8,16 and D = 1 if INDIV = 0, D = 2 if INDIV = 1

    pmctlsetting= PLLM16|PLLD2|SDCKR2_5|DIVEN;
    *pPMCTL= pmctlsetting;

    pmctlsetting|= PLLBP;    //Setting the Bypass bit
    pmctlsetting^= DIVEN;    //Clearing the DIVEN bit
    *pPMCTL= pmctlsetting;    // Putting the PLL into bypass mode

    //Wait for around 4096 cycles for the pll to lock.
    for (i=0; i<5000; i++)
          NOP;

   pmctlsetting = *pPMCTL;
    pmctlsetting ^= PLLBP;          //Clear Bypass Mode
    *pPMCTL = pmctlsetting;

    //Wait for around 15 cycles for the output dividers to stabilize.
     for (i=0; i<16; i++)
          NOP;