[CU]uvm lab6-router

注1:uvm lab1 - __见贤思齐 - 博客园 (cnblogs.com)

注2:uvm lab2 - __见贤思齐 - 博客园 (cnblogs.com)

注3:uvm lab3 - __见贤思齐 - 博客园 (cnblogs.com)

注4:uvm lab4 - __见贤思齐 - 博客园 (cnblogs.com)

注5:uvm lab5 - __见贤思齐 - 博客园 (cnblogs.com)

注6:synopsys uvm1.2 lab guide - IC验证资料 - EETOP 创芯网论坛 (原名：电子顶级开发网) -

注7:uvm1.2 lab链接UVM1.2 Lab验证资料(入门必备) - IC验证资料 - EETOP 创芯网论坛 (原名：电子顶级开发网) -

学习目标

(1) register model的构建与使用;

1.test.sv

(1) config_db::set()或resource_db::set()的使用;

program automatic test;
import uvm_pkg::*;

`include "test_collection.sv"

initial begin
  //interface的config_db::set()/resource_db::set()可以放置到该initial begin end块中;
  uvm_resource_db#(virtual router_io)::set("router_vif","",router_test_top.router_if);
  uvm_resource_db#(virtual reset_io)::set("reset_vif","",router_test_top.reset_if);
  uvm_resource_db#(virtual host_io)::set("host_vif","",router_test_top.host_if);
  uvm_reg::include_coverage("*", UVM_CVR_ALL);
  $timeformat(-9, 1, "ns", 10);
  run_test();
end

endprogram

2.test_collection.sv

(1) hdl_path的config_db::set();

(2) 注意raise_objection与drop_objection的第二个参数;

`ifndef TEST_COLLECTION__SV
`define TEST_COLLECTION__SV

`include "router_env.sv"

class test_base extends uvm_test;
  `uvm_component_utils(test_base)

  router_env env;
  virtual router_io router_vif;
  virtual reset_io  reset_vif;
  virtual host_io   host_vif;
    
  top_reset_sequencer top_reset_sqr;
    
  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    env = router_env::type_id::create("env", this);
    uvm_resource_db#(virtual router_io)::read_by_type("router_vif",router_vif,this);
    uvm_resource_db#(virtual reset_io)::read_by_type("reset_vif",reset_vif,this);

    uvm_config_db#(virtual router_io)::set(this,"env.i_agt[*]","vif",router_vif);
    uvm_config_db#(virtual router_io)::set(this,"env.o_agt[*]","vif",router_vif);
    uvm_config_db#(virtual reset_io)::set(this,"env.r_agt","vif",reset_vif);

    top_reset_sqr=top_reset_sequencer::type_id::create("top_reset_sqr",this);

    uvm_resource_db#(virtual host_io)::read_by_type("host_vif",host_vif,thif);
    uvm_config_db#(virtual host_io)::set(this,"env.h_agt","vif",host_vif);

    uvm_config_db#(uvm_object_wrapper)::set(this,"env.*.sqr.reset_phase", "default_sequence",null);
    uvm_config_db#(uvm_object_wrapper)::set(this,"top_reset_sqr.reset_phase", "default_sequence", top_reset_sequence::get_type());

    uvm_config_db#(string)::set(this,"env","hdl_path","router_test_top.dut");
  endfunction

    virtual function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);

        foreach(env.i_agt[i]) begin
            top_reset_sqqr.pkt_sqr.push_back(env.i_agt[i].sqr);
        end
    
        top_reset_sqr.r_sqr=env.r_agt.sqr;
        top_reset_sqr.h_sqr=env.h_agt.sqr;
    endfunction

    virtual function void end_of_elaboration_phase(uvm_phase phase);
        super.end_of_elaboration_phase(phase);
        env.regmodel.set_coverage(UVM_CVR_ALL);
    endfunction

    virtual task shutdown_phase(uvm_phase phase);
      super.shutdown_phase(phase);
      phase.raise_objection(this);
      env.sb.wait_for_done();
      phase.drop_objection(this);
    endtask: shutdown_phase
        
  virtual function void final_phase(uvm_phase phase);
    super.final_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    if(uvm_report_enabled(UVM_DEBUG, UVM_INFO, "TOPOLOGY")) begin
        uvm_top.print_topology();
    end
    if(uvm_report_enabled(UVM_DEBUG, UVM_INFO, "FACTORY")) begin
        uvm_factory::get().print();
    end
  endfunction
endclass

`include "packet_da_3.sv"

class test_da_3_inst extends test_base;
  `uvm_component_utils(test_da_3_inst)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    set_inst_override_by_type("env.i_agent*.seqr.*", packet::get_type(), packet_da_3::get_type());
  endfunction
endclass

class test_da_3_type extends test_base;
  `uvm_component_utils(test_da_3_type)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    set_type_override_by_type(packet::get_type(), packet_da_3::get_type());
  endfunction
endclass

class test_da_3_seq extends test_base;
  `uvm_component_utils(test_da_3_seq)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    uvm_config_db#(bit[15:0])::set(this, "env.i_agent*.seqr", "da_enable", 16'h0008);
    uvm_config_db#(int)::set(this, "env.i_agent*.seqr", "item_count", 20);
  endfunction
endclass

class test_host_bfm extends test_base;
    `uvm_component_utils(test_host_bfm)
    function new(string name, uvm_component parent);
        super.new(name,parent);
    endfunction

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        uvm_config_db#(uvm_object_wrapper)::set(this,"env.*.configure_phase","default_sequence",null);
        uvm_config_db#(uvm_object_wrapper)::set(this,"env.*.main_phase","default_sequence",null);
        uvm_config_db#(uvm_object_wrapper)::set(this,"env.h_agt.sqr.main_phase","default_sequence",host_bfm_sequence::get_type());
    endfunction: build_phase
endclass: test_host_bfm

class test_host_ral extends test_base;
    `uvm_component_utils(test_host_ral)
    function new(string name, uvm_component parent);
        super.new(name,parent);
    endfunction

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        uvm_config_db#(uvm_object_wrapper)::set(this,"env.*.configure_phase","default_sequence",null);
        uvm_config_db#(uvm_object_wrapper)::set(this,"env.*.main_phase","default_sequence",null);
        uvm_config_db#(uvm_object_wrapper)::set(this,"env.h_agt.sqr.main_phase","default_sequence",host_ral_test_sequence::get_type());
    endfunction: build_phase
endclass: test_host_ral

class test_ral_selftest extends test_base;
    `uvm_component_utils(test_ral_selftest)
    string seq_name="uvm_reg_bit_bash_seq";
    uvm_reg_sequence selftest_seq;
    top_reset_sequence top_reset_seq;

    function new(string name, uvm_component parent);
        super.new(name,parent);
    endfunction

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        uvm_config_db#(uvm_object_wrapper)::set(this,"*","default_sequence",null);
    endfunction: build_phase

    virtual task run_phase(uvm_phase phase);
        phase.raise_objection(this, "starting reset tests");
        top_reset_seq=top_reset_sequence::type_id::create("top_reset_seq",this);
        top_reset_seq.start(top_reset_sqr);
        clp.get_arg_value("+seq=",seq_name);
        $cast(selftest_seq, uvm_factory::get().create_object_by_name(seq_name));
        selftest_seq.model=env.regmodel;
        selftest_seq.start(env.h_agt.sqr);
        phase.drop_objection(this,"Done with register tests");
    endtask: run_phase

endclass: test_ral_selftest

3.router_env.sv

(1) regmodel, adapter, predictor的声明及例化;

(2) connect_phase内,建立regmodel的uvm_reg_map与uvm_reg_adapter, bus_sequencer的联系,建立predictor与uvm_reg_map, uvm_reg_adapter以及bus_agent的联系;

`ifndef ROUTER_ENV__SV
`define ROUTER_ENV__SV

`include "input_agent.sv"
`include "reset_agent.sv"
`include "output_agent.sv"
`include "ms_scoreboard.sv"

`include "host_agent.sv"


class router_env extends uvm_env;
  `uvm_component_utils(router_env)

  reset_agent  r_agent;
  input_agent  i_agent[16];
  scoreboard   sb;
  output_agent o_agent[16];
  host_agent   h_agent;

ral_block_host_regmodel regmodel; //regmodel
reg_adapter  adapter;                //adapter23 
  typedef uvm_reg_predictor #(host_data) hreg_predictor;
hreg_predictor hreg_predictor;       //predictor26 
  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    r_agent = reset_agent::type_id::create("r_agent", this);
    uvm_config_db #(uvm_object_wrapper)::set(this, {r_agent.get_name(), ".", "seqr.reset_phase"}, "default_sequence", reset_sequence::get_type());

    foreach (i_agent[i]) begin
      i_agent[i] = input_agent::type_id::create($sformatf("i_agent[%0d]", i), this);
      uvm_config_db #(int)::set(this, i_agent[i].get_name(), "port_id", i);
      uvm_config_db #(uvm_object_wrapper)::set(this, {i_agent[i].get_name(), ".", "seqr.main_phase"}, "default_sequence", router_input_port_reset_sequence::get_type());
      uvm_config_db #(uvm_object_wrapper)::set(this, {i_agent[i].get_name(), ".", "seqr.main_phase"}, "default_sequence", packet_sequence::get_type());
    end

    sb = scoreboard::type_id::create("sb", this);

    foreach (o_agent[i]) begin
      o_agent[i] = output_agent::type_id::create($sformatf("o_agent[%0d]",i),this);
      uvm_config_db #(int)::set(this, o_agent[i].get_name(), "port_id", i);
    end

    h_agent = host_agent::type_id::create("h_agent", this);
    adapter = reg_adapter::type_id::create("adapter",this);        //adapter的例化;55 
    uvm_config_db #(ral_block_host_regmodel)::get(this, "", "regmodel", regmodel);

    if (regmodel == null) begin
      string hdl_path;
      if (!uvm_config_db #(string)::get(this, "", "hdl_path", hdl_path)) begin
        `uvm_warning("HOSTCFG", "HDL path for backdoor not set!");
      end
      regmodel = ral_block_host_regmodel::type_id::create("regmodel", this);
      regmodel.build();
      regmodel.lock_model();
      regmodel.set_hdl_path_root(hdl_path);
    end

    uvm_config_db#(ral_block_host_regmodel)::set(this, h_agt.get_name(), "regmodel", regmodel);
    uvm_config_db#(uvm_object_wrapper)::set(this,{h_agt.get_name(), ".", "sqr.configure_phase"}, "default_sequence", ral_port_unlock_sequence::get_type());
    hreg_predict=hreg_predictor::type_id::create("h_reg_predict",this);   //predictor的例化;
  endfunction

  virtual function void connect_phase(uvm_phase phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    foreach (i_agent[i]) begin
      i_agent[i].analysis_port.connect(sb.before_export);
    end
    foreach (o_agent[i]) begin
      o_agent[i].analysis_port.connect(sb.after_export);
    end

regmodel.default_map.set_sequencer(h_agent.seqr, adapter);

    regmodel.default_map.set_auto_predict(0);
    hreg_predict.map=regmodel.get_default_map();
    hreg_predict.adapter=adapter;
    h_agt.analysis_port.connect(hreg_predict.bus_in);
  endfunction
endclass

`endif

4.top_reset_sequence.sv

class top_reset_sequence extends uvm_sequence;
    `uvm_object_utils(top_reset_sequence)
    `uvm_declare_p_sequencer(top_reset_sequencer)

    reset_sequence  r_seq;
    router_input_port_reset_sequence i_seq;
    host_reset_sequence h_seq;
    uvm_event reset_event=uvm_event_pool::get_global("reset");

    function new(string name="top_reset_sequence");
        super.new(name);
        `uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
        `ifdef UVM_POST_VERSION_1_1
        set_automatic_phase_objection(1);
        `endif
    endfunction

    virtual task body();
        `uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
        fork
            `uvm_do_on(r_seq,p_sequencer.r_sqr);
            foreach(p_sequencer.pkt_sqr[i]) begin
                fork
                    int j=i;
                    begin
                        reset_event.wait_on();//该处采用了wait_on()而不是wait_trigger,与sequence和driver行为相关;
                        `uvm_do_on(i_seq,p_sequencer.pkt_sqr[j]);
                    end
                join_none
            end
            begin
                reset_event.wait_on();
                `uvm_do_on(h_seq, p_sequencer.h_sqr)
            end
        join
    endtask

    `ifdef UVM_VERSION_1_1
    virtual task pre_start();
        `uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
        if((get_parent_sequence()==null) && (starting_phase!=null))
            starting_phase.raise_objection(this);
    endtask
    virtual task post_start();
        `uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
        if((get_parent_sequence()==null) && (starting_phase!=null))
            starting_phase.raise_objection(this);
    endtask
    `endif
endclass

5.host_data & reg_adapter

5.1 host_data

class host_data extends uvm_sequence_item;
  typedef enum {READ, WRITE} kind_e;
  rand kind_e    kind;
    rand uvm_status_e status;
  rand bit[15:0] addr;
  rand bit[15:0] data;
 
  `uvm_object_utils_begin(host_data)
    `uvm_field_int(addr, UVM_ALL_ON)
    `uvm_field_int(data, UVM_ALL_ON)
    `uvm_field_enum(kind_e, kind, UVM_ALL_ON)
        `uvm_field_enum(uvm_status_e, status, UVM_ALL_ON)
  `uvm_object_utils_end

  function new(string name="host_data");
    super.new(name);
    `uvm_info("Trace", $sformatf("%m"), UVM_HIGH);
        status.rand_mode(0);
  endfunction
endclass

5.2 reg_adapter

class reg_adapter extends uvm_reg_adapter;
  `uvm_object_utils(reg_adapter)

  function new(string name="reg_adapter");
    super.new(name);
    `uvm_info("Trace", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
    host_data tr;
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    tr = host_data::type_id::create("tr");
    tr.kind = (rw.kind == UVM_READ) ? host_data::READ : host_data::WRITE;
    tr.addr = rw.addr;
    tr.data = rw.data;
    return tr;

  endfunction

  virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
    host_data tr;
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    if (!$cast(tr, bus_item)) begin
      `uvm_fatal("NOT_HOST_REG_TYPE", "bus_item is not correct type");
    end
    rw.kind = (tr.kind == host_data::READ) ? UVM_READ : UVM_WRITE;
    rw.addr = tr.addr;
    rw.data = tr.data;
    rw.status = tr.status;

  endfunction
endclass

6.host_sequences

6.1host_sequence_base

class host_sequence_base extends uvm_sequence #(host_data);
  `uvm_object_utils(host_sequence_base)
    
    virtual host_io vif;
    uvm_sequencer_base p_sqr;

  function new(string name = "host_sequence_base");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

    virtual task pre_start();
        p_sqr=get_sequencer();
        ...
  endtask
    
  ...
endclass

6.2host_reset_sequence

class host_reset_sequence extends host_sequence_base;
    `uvm_object_utils(host_reset_sequence)

    function new(string name="host_reset_sequence");
        super.new(name);
    endfunction

    virtual task body();
        vif.wr_n = 1'b1;
        vif.rd_n = 1'b1;
        vif.address = 'z;
        vif.data = 'z;
    endtask

endclass

6.3host_bfm_sequence

class host_bfm_sequence extends host_sequence_base;
  `uvm_object_utils(host_bfm_sequence)

  function new(string name = "host_bfm_sequence");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual task body();
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    `uvm_do_with(req, {addr == 'h0; kind == host_data::READ;});

    if(req.data != 'h5a03) begin
        `uvm_fatal("BFM_ERR",$sformatf("HOST_ID is %4h instead of 'h5a03",req.data))
    end

    `uvm_do_with(req, {addr == 'h100; kind == host_data::READ;});

    if(req.data != '1) begin
         `uvm_fatal("BFM_ERR",$sformatf("HOST_ID is %4h instead of 'hffff",req.data))
    end

    `uvm_do_with(req, {addr == 'h100; data == '0; kind == host_data::WRITE;});
    `uvm_do_with(req, {addr == 'h100; kind == host_data::READ;});

    if(req.data != '0) begin
        `uvm_fatal("BFM_ERR",$sformatf("HOST_ID is %4h instead of 'h0000",req.data))
    end

  endtask

endclass

6.4host_ral_sequence_base

（1）uvm_reg_sequence内通过config_db::set()方法获取regmodel的句柄;

class host_ral_sequence_base extends uvm_reg_sequence #(host_sequence_base);
  `uvm_object_utils(host_ral_sequence_base)
  ral_block_host_regmodel regmodel;

  function new(string name = "host_ral_sequence_base");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual task pre_start();
        super.pre_start();
        if(!uvm_config_db#(ral_block_host_regmodel)::get(p_sqr.get_parent(),"","regmodel", regmodel)) begin
            `uvm_info("RAL_CFG","regmodel not set through configureation.",UVM_MEDIUM)
            if(regmodel==null) begin
                `uvm_fatal("RAL_CFG","regmodel not set")
            end
        end
    endtask
endclass

6.5host_ral_test_sequence

class host_ral_test_sequence extends host_ral_sequence_base;
    `uvm_object_utils(host_ral_test_sequence)
    
    function new(string name="host_ral_test_sequence");
        super.new(name);
    endfunction

    virtual task body();
        uvm_status_e status;
        uvm_reg_data_t data;

        regmodel.HOST_ID.read(.status(status), .value(data), .path(UVM_BACKDOOR), .parent(this));
      ...
    endtask
endclass

7.reset_sequence.sv & reset_agent.sv(省略,见uvm lab5)

8.input_agent.sv & iMonitor.sv & driver.sv(省略)

9.output_agent.sv & oMonitor.sv(省略)

10.scoreboard.sv & ms_scoreboard.sv(省略)

11.host_agent.sv & host_driver.sv & host_monitor.sv & host_sequencer.sv

`ifndef HOST_AGENT__SV
`define HOST_AGENT__SV

`include "host_sequence.sv"

typedef uvm_sequencer #(host_data) host_sequencer;
typedef class host_driver;
typedef class host_monitor;

class host_agent extends uvm_agent;
  virtual host_io sigs;     // DUT host interface
  uvm_analysis_port #(host_data) analysis_port;
  host_sequencer seqr;
  host_driver    drv;
  host_monitor   mon;

  `uvm_component_utils(host_agent)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    // The agent retrieves virtual interface.
    uvm_config_db#(virtual host_io)::get(this, "", "host_io", sigs);

    if (is_active) begin
      seqr = host_sequencer::type_id::create("seqr", this);
      drv  = host_driver::type_id::create("drv", this);
      uvm_config_db#(virtual host_io)::set(this, "drv", "host_io", sigs);
      uvm_config_db#(virtual host_io)::set(this, "seqr", "host_io", sigs);
    end
    mon = host_monitor::type_id::create("mon", this);
    uvm_config_db#(virtual host_io)::set(this, "mon", "host_io", sigs);
  endfunction

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    if (is_active) begin
      drv.seq_item_port.connect(seqr.seq_item_export);
    end
  endfunction
endclass

class host_driver extends uvm_driver #(host_data);
  virtual host_io sigs;
  event go;

  `uvm_component_utils(host_driver)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    if (!uvm_config_db#(virtual host_io)::get(this, "", "host_io", sigs)) begin
      `uvm_fatal("CFGERR", "DUT host interface not set");
    end
  endfunction

  virtual task pre_reset_phase(uvm_phase phase);
    sigs.wr_n    = 'x;
    sigs.address = 'x;
    sigs.data    = 'x;
  endtask

  virtual task reset_phase(uvm_phase phase);
    sigs.wr_n    = '1;
    sigs.address = '1;
    sigs.data    = '1;
  endtask

  virtual task post_reset_phase(uvm_phase phase);
//    -> go;
  endtask

  virtual task run_phase(uvm_phase phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
//    suspend();
    forever begin
      seq_item_port.get_next_item(req);
      `uvm_info("RUN", { "Before process\n", req.sprint() }, UVM_FULL);
      data_rw(req);
      `uvm_info("RUN", { "After process\n", req.sprint() }, UVM_FULL);
      seq_item_port.item_done();
    end
  endtask

  virtual task data_rw(host_data req);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    case(req.kind)
      host_data::READ: begin
                        sigs.wr_n = '1;
                        sigs.cb.address <= req.addr;
                        @(sigs.cb);
                        req.data = sigs.cb.data;
                    end
      host_data::WRITE: begin
                         sigs.wr_n = '0;
                         sigs.data = req.data;
                         sigs.cb.address <= req.addr;
                         @(sigs.cb);
                         sigs.wr_n = '1;
                         sigs.data = 'z;
                       end
      default: begin `uvm_fatal("REGERR", "Not a valid Register Command"); end
    endcase
  endtask

  task suspend();
    wait(go.triggered);
  endtask
endclass

class host_monitor extends uvm_monitor;
  uvm_analysis_port #(host_data) analysis_port;
  virtual host_io sigs;
  event go;

  `uvm_component_utils(host_monitor)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    if (!uvm_config_db#(virtual host_io)::get(this, "", "host_io", sigs)) begin
      `uvm_fatal("CFGERR", "DUT host interface not set");
    end
    analysis_port = new("analysis_port", this);
  endfunction

  virtual task run_phase(uvm_phase phase);
    host_data tr;
    suspend();
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    forever begin
      tr = host_data::type_id::create("tr", this);
      data_rw(tr);
      analysis_port.write(tr);
    end
  endtask

  virtual task post_reset_phase(uvm_phase phase);
    -> go;
  endtask

  virtual task data_rw(host_data tr);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    if(!sigs.mon.wr_n) begin
      tr.kind = host_data::WRITE;
      tr.addr = sigs.mon.address;
      tr.data = sigs.mon.data;
      `uvm_info("Got WRITE", {"\n", tr.sprint()}, UVM_DEBUG);
      @(sigs.mon);
    end else begin
      fork
        begin
          fork
            @(sigs.mon.wr_n);
            @(sigs.mon.address);
          join_any
          disable fork;
          tr.addr = sigs.mon.address;
          tr.data = sigs.mon.data;
          if(!sigs.mon.wr_n) begin
            tr.kind = host_data::WRITE;
            `uvm_info("Got WRITE", {"\n", tr.sprint()}, UVM_DEBUG);
          end else begin
            tr.kind = host_data::READ;
            `uvm_info("Got READ", {"\n", tr.sprint()}, UVM_DEBUG);
          end
          @(sigs.mon);
        end
      join
    end
  endtask

  task suspend();
    wait(go.triggered);
  endtask
endclass

`endif

12.host.ralf

# This file contains the DUT register and memory definitions

#
# Lab 7 - Task 6
# Populate each of the following register and memory specification.
#
register HOST_ID {
#  ToDo
  field REV_ID {
    bits 8;
    access ro;
    reset 'h03;
  }
  field CHIP_ID {
    bits 8;
    access ro;
    reset 'h5A;
  }
}

register PORT_LOCK {
#  ToDo
  field LOCK {
    bits 16;
    access w1c;
    reset 'hffff;
  }
}

register REG_ARRAY {
#  ToDo
  field USER_REG {
    bits 16;
    access rw;
    reset 'h0;
  }
}

memory RAM {
#  ToDo
  size 4k;
  bits 16;
  access rw;
}

#
# The block level declaration is done for you.  This include the hdl_path name for
# the signals in the DUT.  Later on, the hdl_path will be in RAL backdoor access.
#
block host_regmodel {
  bytes 2;
  register HOST_ID        (host_id)       @'h0000;
  register PORT_LOCK      (lock)          @'h0100;
  register REG_ARRAY[256] (host_reg[%d])  @'h1000; # array must specify HDL index
  memory   RAM            (ram)           @'h4000;
}

13.ral_host_regmodel.sv

(1) uvm_reg和uvm_reg_model的定义;

(2) add_hdl_path(), add_reg(), add_mem()的使用;

 

 

 

`ifndef RAL_HOST_REGMODEL
`define RAL_HOST_REGMODEL

import uvm_pkg::*;

class ral_reg_HOST_ID extends uvm_reg;
    uvm_reg_field REV_ID;
    uvm_reg_field CHIP_ID;

    function new(string name = "HOST_ID");
        super.new(name, 16,build_coverage(UVM_NO_COVERAGE));
    endfunction: new
   virtual function void build();
      this.REV_ID = uvm_reg_field::type_id::create("REV_ID");
      this.REV_ID.configure(this, 8, 0, "RO", 0, 8'h03, 1, 0, 1);
      this.CHIP_ID = uvm_reg_field::type_id::create("CHIP_ID");
      this.CHIP_ID.configure(this, 8, 8, "RO", 0, 8'h5A, 1, 0, 1);
   endfunction: build

    `uvm_object_utils(ral_reg_HOST_ID)

endclass : ral_reg_HOST_ID


class ral_reg_PORT_LOCK extends uvm_reg;
    rand uvm_reg_field LOCK;

    function new(string name = "PORT_LOCK");
        super.new(name, 16,build_coverage(UVM_NO_COVERAGE));
    endfunction: new
   virtual function void build();
      this.LOCK = uvm_reg_field::type_id::create("LOCK");
      this.LOCK.configure(this, 16, 0, "W1C", 0, 16'hffff, 1, 0, 1);
   endfunction: build

    `uvm_object_utils(ral_reg_PORT_LOCK)

endclass : ral_reg_PORT_LOCK


class ral_reg_REG_ARRAY extends uvm_reg;
    rand uvm_reg_field USER_REG;

    function new(string name = "REG_ARRAY");
        super.new(name, 16,build_coverage(UVM_NO_COVERAGE));
    endfunction: new
   virtual function void build();
      this.USER_REG = uvm_reg_field::type_id::create("USER_REG");
      this.USER_REG.configure(this, 16, 0, "RW", 0, 16'h0, 1, 0, 1);
   endfunction: build

    `uvm_object_utils(ral_reg_REG_ARRAY)

endclass : ral_reg_REG_ARRAY


class ral_mem_RAM extends uvm_mem;
   function new(string name = "RAM");
      super.new(name, `UVM_REG_ADDR_WIDTH'h1000, 16, "RW", build_coverage(UVM_NO_COVERAGE));
   endfunction
   virtual function void build();
   endfunction: build

   `uvm_object_utils(ral_mem_RAM)

endclass : ral_mem_RAM


class ral_block_host_regmodel extends uvm_reg_block;
    rand ral_reg_HOST_ID HOST_ID;
    rand ral_reg_PORT_LOCK PORT_LOCK;
    rand ral_reg_REG_ARRAY REG_ARRAY[256];
    rand ral_mem_RAM RAM;
    uvm_reg_field HOST_ID_REV_ID;
    uvm_reg_field REV_ID;
    uvm_reg_field HOST_ID_CHIP_ID;
    uvm_reg_field CHIP_ID;
    rand uvm_reg_field PORT_LOCK_LOCK;
    rand uvm_reg_field LOCK;
    rand uvm_reg_field REG_ARRAY_USER_REG[256];
    rand uvm_reg_field USER_REG[256];

    function new(string name = "host_regmodel");
        super.new(name, build_coverage(UVM_NO_COVERAGE));
    endfunction: new

   virtual function void build();
      this.default_map = create_map("", 0, 2, UVM_LITTLE_ENDIAN);
      this.HOST_ID = ral_reg_HOST_ID::type_id::create("HOST_ID");
      this.HOST_ID.build();
      this.HOST_ID.configure(this, null, "");
      this.HOST_ID.add_hdl_path('{

            '{"host_id", -1, -1}
      });
      this.default_map.add_reg(this.HOST_ID, `UVM_REG_ADDR_WIDTH'h0, "RW", 0);
      this.HOST_ID_REV_ID = this.HOST_ID.REV_ID;
      this.REV_ID = this.HOST_ID.REV_ID;
      this.HOST_ID_CHIP_ID = this.HOST_ID.CHIP_ID;
      this.CHIP_ID = this.HOST_ID.CHIP_ID;
      this.PORT_LOCK = ral_reg_PORT_LOCK::type_id::create("PORT_LOCK");
      this.PORT_LOCK.build();
      this.PORT_LOCK.configure(this, null, "");
      this.PORT_LOCK.add_hdl_path('{

            '{"lock", -1, -1}
      });
      this.default_map.add_reg(this.PORT_LOCK, `UVM_REG_ADDR_WIDTH'h100, "RW", 0);
      this.PORT_LOCK_LOCK = this.PORT_LOCK.LOCK;
      this.LOCK = this.PORT_LOCK.LOCK;
      foreach (this.REG_ARRAY[i]) begin
         int J = i;
         this.REG_ARRAY[J] = ral_reg_REG_ARRAY::type_id::create($psprintf("REG_ARRAY[%0d]",J));
         this.REG_ARRAY[J].build();
         this.REG_ARRAY[J].configure(this, null, "");
         this.REG_ARRAY[J].add_hdl_path('{

            '{$psprintf("host_reg[%0d]", J), -1, -1}
         });
         this.default_map.add_reg(this.REG_ARRAY[J], `UVM_REG_ADDR_WIDTH'h1000+J*`UVM_REG_ADDR_WIDTH'h1, "RW", 0);
         this.REG_ARRAY_USER_REG[J] = this.REG_ARRAY[J].USER_REG;
         this.USER_REG[J] = this.REG_ARRAY[J].USER_REG;
      end
      this.RAM = ral_mem_RAM::type_id::create("RAM");
      this.RAM.build();
      this.RAM.configure(this, "ram");
      this.default_map.add_mem(this.RAM, `UVM_REG_ADDR_WIDTH'h4000, "RW", 0);
   endfunction : build

   `uvm_object_utils(ral_block_host_regmodel)

endclass : ral_block_host_regmodel



`endif