[CU]uvm lab5.1-router(不推荐)

注1:uvm lab1 - __见贤思齐 - 博客园 (cnblogs.com)

注2:uvm lab2 - __见贤思齐 - 博客园 (cnblogs.com)

注3:uvm lab3 - __见贤思齐 - 博客园 (cnblogs.com)

注4:uvm lab4 - __见贤思齐 - 博客园 (cnblogs.com)

注5:uvm lab5 - __见贤思齐 - 博客园 (cnblogs.com)

学习目标

(1) uvm_seq_lib的使用;

1.test.sv

program automatic test;
import uvm_pkg::*;

`include "test_collection.sv"

initial begin
  $timeformat(-9, 1, "ns", 10);
  run_test();
end

endprogram

2.test_collection.sv

`ifndef TEST_COLLECTION__SV
`define TEST_COLLECTION__SV

`include "router_env.sv"

class test_base extends uvm_test;
  `uvm_component_utils(test_base)

  router_env env;

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    env = router_env::type_id::create("env", this);
    uvm_config_db#(virtual router_io)::set(this, "env.i_agent[*]", "router_io", router_test_top.sigs);
    uvm_config_db#(virtual router_io)::set(this, "env.o_agent[*]", "router_io", router_test_top.sigs);
    uvm_config_db#(virtual router_io)::set(this, "env.r_agent", "router_io", router_test_top.sigs);

    // Lab 6 - Task 5, Step 2
    // There are three ways to register sequences into a sequence library:
    //
    // 1 - Use `uvm_add_to_seq_lib() macro
    // 2 - Use the sequence library class's add_typewide_sequence() method
    // 3 - Use the sequence library object's add_sequence() method
    //
    // There are different consequences with each of these mechanisms.
    //
    // The `uvm_add_to_seq_lib() macro will add the sequence to the sequence library for all tests.
    //
    // The add_typewide_sequence() method will add the sequence to the sequence library only
    // for the test that called the method.
    //
    // The add_sequence() method, requires that an instance of the sequence library be constructed.
    // Then, the add_sequence() method called via this sequence library handle will only affect
    // the sequencer that's configured to use this particular sequence library object.
    //
    // For this lab, use the add_typewide_sequence() method in the test_base class to add the
    // packet_sequence to the packet_seq_lib.
    //
    // ToDo
    packet_seq_lib::add_typewide_sequence(packet_sequence::get_type());

  endfunction

  virtual function void final_phase(uvm_phase phase);
    super.final_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    uvm_top.print_topology();
    uvm_factory::get().print();
  endfunction
endclass

`include "packet_da_3.sv"

class test_da_3_inst extends test_base;
  `uvm_component_utils(test_da_3_inst)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    set_inst_override_by_type("env.i_agent*.seqr.*", packet::get_type(), packet_da_3::get_type());
  endfunction
endclass

class test_da_3_type extends test_base;
  `uvm_component_utils(test_da_3_type)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    set_type_override_by_type(packet::get_type(), packet_da_3::get_type());
  endfunction
endclass

class test_da_3_seq extends test_base;
  `uvm_component_utils(test_da_3_seq)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    uvm_config_db#(bit[15:0])::set(this, "env.i_agent*.seqr", "da_enable", 16'h0008);
    uvm_config_db#(int)::set(this, "env.i_agent*.seqr", "item_count", 20);
  endfunction
endclass


// Lab 6 - Task 7, Step 2
// Create a test class called test_seq_lib_cfg extended from test_base.
//
// Within the class, create an instance of uvm_sequence_library_cfg, call it seq_cfg.
//
// ToDo
class test_seq_lib_cfg extends test_base;
  uvm_sequence_library_cfg seq_cfg;
  `uvm_component_utils(test_seq_lib_cfg)
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction


// Lab 6 - Task 7, Step 3
//
// Define a build phase in which the seq_cfg object is constructed with UVM_SEQ_LIB_RAND mode
// and the max_random_count and the min_random_count to 1.
//
// Then, configure all the agent sequencer's sequence library to use this configuration.
//
// ToDo
  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    seq_cfg = new("seq_cfg", UVM_SEQ_LIB_RAND, 1, 1);
    uvm_config_db #(uvm_sequence_library_cfg)::set(this, "env.i_agent*.seqr.main_phase", "default_sequence.config", seq_cfg);
  endfunction
endclass


`endif

3.router_env.sv

`ifndef ROUTER_ENV__SV
`define ROUTER_ENV__SV

`include "input_agent.sv"
`include "reset_agent.sv"
`include "output_agent.sv"
`include "ms_scoreboard.sv"


class router_env extends uvm_env;
  input_agent  i_agent[16];
  scoreboard   sb;
  output_agent o_agent[16];
  reset_agent  r_agent;


  `uvm_component_utils(router_env)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    foreach (i_agent[i]) begin
      i_agent[i] = input_agent::type_id::create($sformatf("i_agent[%0d]", i), this);
      uvm_config_db #(int)::set(this, i_agent[i].get_name(), "port_id", i);

      // Lab 6 - Task 4, Step 2
      // Replace the following configuration of the sequencers to use the sequence library
      // (packet_seq_lib) instead of packet sequence (packet_sequence):
      //
      // ToDo
      uvm_config_db #(uvm_object_wrapper)::set(this, {i_agent[i].get_name(), ".", "seqr.main_phase"}, "default_sequence", packet_seq_lib::get_type());
      //uvm_config_db #(uvm_object_wrapper)::set(this, {i_agent[i].get_name(),".sqr.reset_phase"}, "default_sequence", router_input_port_reset_sequence::get_type());
    end

    sb = scoreboard::type_id::create("sb", this);
    foreach (o_agent[i]) begin
      o_agent[i] = output_agent::type_id::create($sformatf("o_agent[%0d]",i),this);
      uvm_config_db #(int)::set(this, o_agent[i].get_name(), "port_id", i);
    end

    r_agent = reset_agent::type_id::create("r_agent", this);
    uvm_config_db #(uvm_object_wrapper)::set(this, {r_agent.get_name(), ".", "seqr.reset_phase"}, "default_sequence", reset_sequence::get_type());
  endfunction

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    foreach (i_agent[i]) begin
      i_agent[i].analysis_port.connect(sb.before_export);
    end
    foreach (o_agent[i]) begin
      o_agent[i].analysis_port.connect(sb.after_export);
    end
  endfunction

endclass

`endif

4.input_agent.sv

(1) 与lab5中input_agent.sv相同;

4.1driver.sv

(1) 与lab5中driver.sv相同;

4.2iMonitor.sv

(1) 与lab5中iMonitor.sv相同;

5.output_agent.sv

(1) 与lab5中output_agent.sv相同;

5.1oMonitor.sv

(1) 与lab5中oMonitor.sv相同;

6.reset_agent.sv

(1) 与lab5中reset_agent.sv相同;

7.ms_scoreboard.sv

(1) 与lab5中ms_scoreboard.sv相同;

8.packet_seq_lib_pkg.sv

// Lab 6 - Task 2, Step 2
//
// Declare a package called packet_seq_lib_pkg.
// package packet_seq_lib_pkg;
//
// ToDo
package packet_seq_lib_pkg;


// Lab 6 - Task 2, Step 3
//
// Import the uvm_pkg package.
// import uvm_pkg::*;
//
// ToDo
import uvm_pkg::*;


//
// The packet class is moved inside the package.
//
class packet extends uvm_sequence_item;
  rand bit[3:0] sa, da;
  rand bit[7:0] payload[$];

  `uvm_object_utils_begin(packet)
    `uvm_field_int(sa, UVM_ALL_ON | UVM_NOCOMPARE)
    `uvm_field_int(da, UVM_ALL_ON)
    `uvm_field_queue_int(payload, UVM_ALL_ON)
  `uvm_object_utils_end

  constraint valid {
    payload.size inside {[1:10]};
  }

  function new(string name="packet");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)
  endfunction
endclass

// Lab 6 - Task 2, Step 4
//
// Every sequencen library that you create will have the identical structure.
// The only thing that changes is the name of the class and the sequence item type.
//
// The uvm_sequence_library_utils macro creates the infrastructure for the sequence
// library class.  The macro and the init_sequence_library() call are required to
// to be able to populate the sequence library with sequences are registered
// with it or any of its base classes.
//
// Create the packet sequence library as follows:
//
// class packet_seq_lib extends uvm_sequence_library #(packet);
//   `uvm_object_utils(packet_seq_lib)
//   `uvm_sequence_library_utils(packet_seq_lib)
//
//   function new(string name = "packet_seq_lib");
//     super.new(name);
//     `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
//     init_sequence_library();
//   endfunction
// endclass
//
// ToDo
class packet_seq_lib extends uvm_sequence_library #(packet);
`uvm_object_utils(packet_seq_lib)
`uvm_sequence_library_utils(packet_seq_lib)

  function new(string name = "packet_seq_lib");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    init_sequence_library();
  endfunction
endclass


endpackage

8.1packet_sequence.sv

`ifndef PACKET_SEQUENCE__SV
`define PACKET_SEQUENCE__SV

// Lab 6 - Task 3, Step 2
// The packet class now resides inside the packet sequence library package.
//
// Replace the following include statement with an import of the packet sequence library package:
// import packet_seq_lib_pkg::*;
//
// ToDo
import packet_seq_lib_pkg::*;


class packet_sequence extends uvm_sequence #(packet);
  int       item_count = 10;
  int       port_id    = -1;
  bit[15:0] da_enable  = '1;
  int       valid_da[$];

  `uvm_object_utils_begin(packet_sequence)
    `uvm_field_int(item_count, UVM_ALL_ON)
    `uvm_field_int(port_id, UVM_ALL_ON)
    `uvm_field_int(da_enable, UVM_ALL_ON)
    `uvm_field_queue_int(valid_da, UVM_ALL_ON)
  `uvm_object_utils_end

  function void pre_randomize();
    uvm_config_db#(int)::get(m_sequencer, "", "item_count", item_count);
    uvm_config_db#(int)::get(m_sequencer, "", "port_id", port_id);
    uvm_config_db#(bit[15:0])::get(m_sequencer, "", "da_enable", da_enable);
    if (!(port_id inside {-1, [0:15]})) begin
      `uvm_fatal("CFGERR", $sformatf("Illegal port_id value of %0d", port_id));
    end

    valid_da.delete();
    for (int i=0; i<16; i++)
      if (da_enable[i])
        valid_da.push_back(i);
  endfunction

  function new(string name = "packet_sequence");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual task body();

    // Lab 6 - Task 3, Step 3
    // Create a parent sequence handle, call it parent.
    // 
    // uvm_sequence_base parent;
    //
    // ToDo
    uvm_sequence_base parent;


    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    uvm_config_db#(int)::get(m_sequencer, "*", "item_count", item_count);

    // Lab 6 - Task 3, Step 4 and 5
    // Call get_parent_sequence() to retrive the parent sequence handle.
    //
    // If parent handle is not null, set the sequence's start_phase to parent
    // sequence's starting_phase.
    //
    // This is necessary, because child sequences do not have start_phase of their own.
    // 
    // parent = get_parent_sequence();
    // if (parent != null) begin
    //   starting_phase = parent.starting_phase;
    // end
    //
    // ToDo
    parent = get_parent_sequence();
    if (parent != null) begin
      starting_phase = parent.starting_phase;
    end


    if (starting_phase != null) begin
      uvm_objection objection = starting_phase.get_objection();
      objection.set_drain_time(this, 1us);
      starting_phase.raise_objection(this);
    end

    repeat(item_count) begin
      `uvm_do_with(req, {if (port_id == -1) sa inside {[0:15]}; else sa == port_id; da inside valid_da;});
    end

    if (starting_phase != null) begin
      starting_phase.drop_objection(this);
    end
 endtask

endclass

`endif

8.2packet.sv

(1) 与lab5中packet.sv相同;

8.3packet_da_3.sv

(1) 与lab5中packet_da_3.sv相同;

9.reset相关的sequence

9.1reset_sequencer.sv

9.2router_input_port_reset_sequence.sv

10.top_reset_sequencer.sv & top_reset_sequence.sv

10.1top_reset_sequencer.sv

10.2top_reset_sequence.sv