[CU]uvm lab4-router

注1:uvm lab1 - __见贤思齐 - 博客园 (cnblogs.com)

注2:uvm lab2 - __见贤思齐 - 博客园 (cnblogs.com)

注3:uvm lab3 - __见贤思齐 - 博客园 (cnblogs.com)

注4:IC仿真makefile示例4 - __见贤思齐 - 博客园 (cnblogs.com)

注5:结合synopsys uvm lab guide阅读;

注6:uvm1.1 lab链接第三方资源 – 路科验证 (rockeric.com).

注7:synopsys uvm1.2 lab guide - IC验证资料 - EETOP 创芯网论坛 (原名：电子顶级开发网) -

注8:uvm1.2 lab链接UVM1.2 Lab验证资料(入门必备) - IC验证资料 - EETOP 创芯网论坛 (原名：电子顶级开发网) -

学习目标

(1) 添加virtual interface的使用;

1.test.sv

program automatic test;
import uvm_pkg::*;

`include "test_collection.sv"

initial begin
  $timeformat(-9, 1, "ns", 10);
  run_test();
end

endprogram

2.router_test_top.sv

module router_test_top;
  parameter simulation_cycle = 100 ;
  bit  SystemClock;

  router_io sigs(SystemClock);
  host_io   host(SystemClock);
  router    dut(sigs, host);

  initial begin
    forever #(simulation_cycle/2) SystemClock = ~SystemClock ;
  end
endmodule  

2.1 router_io.sv (interface的使用)

`ifndef ROUTER_IO__SV
`define ROUTER_IO__SV

interface router_io(input bit clk);

   logic  reset_n ;
   logic [15:0] frame_n ;
   logic [15:0] valid_n ;
   logic [15:0] din ;
   logic [15:0] dout ;
   logic [15:0] busy_n ;
   logic [15:0] valido_n ;
   logic [15:0] frameo_n ;

   clocking drvClk @(posedge clk);
      output  reset_n;
      output  frame_n;
      output  valid_n;
      output  din;
      input   busy_n;
   endclocking: drvClk

   clocking iMonClk @(posedge clk);
      input  frame_n;
      input  valid_n;
      input  din;
      input  busy_n;
   endclocking: iMonClk

   clocking oMonClk @(posedge clk);
      input  dout;
      input  valido_n;
      input  frameo_n;
   endclocking: oMonClk

   modport driver(clocking drvClk, output reset_n);
   modport imon(clocking iMonClk);
   modport omon(clocking oMonClk);
   modport dut(input clk, reset_n, frame_n, valid_n, din, output dout, busy_n, valido_n, frameo_n);

endinterface: router_io

`endif

2.2 host_io.sv (interface的使用)

`ifndef HOST_IO__SV
`define HOST_IO__SV
interface host_io(input logic clk);
  logic        wr_n;
  logic [15:0] address;
  wire  [15:0] data;

  clocking cb @(posedge clk);
    inout   data;
    output  address;
    output  wr_n;
  endclocking

  clocking mon @(posedge clk);
    input  data;
    input  address;
    input  wr_n;
  endclocking

  modport dut(input clk, input wr_n, address, inout data);
endinterface: host_io
`endif

3.test_collection.sv(派生于uvm_test)

`ifndef TEST_COLLECTION__SV
`define TEST_COLLECTION__SV

`include "router_env.sv"

class test_base extends uvm_test;
  `uvm_component_utils(test_base)

  router_env env;
  //virtual router_io router_vif,reset_vif;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    env = router_env::type_id::create("env", this);

    // Lab 4 - Task 5, Step 3
    //
    // Configure the router environment agents' virtual interface by using SystemVerilog's
    // cross module reference (XMR) to access the interface
    //
    // At the test level, configuration of components dedicated to a DUT interface should be done via
    // the agent connected to that interface.  The test developer should treat the agent as the
    // Bus Functional Model (BFM) for the interface without needing to know anything about the
    // sub-components of the agent.
    //
    // uvm_config_db#(virtual router_io)::set(this, "env.i_agent", "router_io", router_test_top.sigs);
    // uvm_config_db#(virtual router_io)::set(this, "env.r_agent", "router_io", router_test_top.sigs);
    //
    // ToDo
    uvm_config_db#(virtual router_io)::set(this, "env.i_agent", "router_io", router_test_top.sigs);
    uvm_config_db#(virtual router_io)::set(this, "env.r_agent", "router_io", router_test_top.sigs);
    //注1:可以在test_base中声明virtual router_io router_vif与virtual router_io reset_vif;在test.sv中进行config_db::set(),在test_base中进行config_db::get(),然后config_db::set()给test_base的子组件;
    //uvm_resource_db#(virtual router_io)::read_by_type("router_vif",router_vif,this); 
    //uvm_config_db#(virtual router_io)::set(this,"env.i_agt","vif",router_vif);
    //reset_vif与router_vif仿照line38-39做同样处理;
  endfunction

  virtual function void final_phase(uvm_phase phase);
    super.final_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    uvm_top.print_topology();

    uvm_factory::get().print();
  endfunction
endclass

`include "packet_da_3.sv"

class test_da_3_inst extends test_base;
  `uvm_component_utils(test_da_3_inst)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    set_inst_override_by_type("env.i_agent*.seqr.*", packet::get_type(), packet_da_3::get_type());
  endfunction
endclass

class test_da_3_type extends test_base;
  `uvm_component_utils(test_da_3_type)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    set_type_override_by_type(packet::get_type(), packet_da_3::get_type());
  endfunction
endclass

class test_da_3_seq extends test_base;
  `uvm_component_utils(test_da_3_seq)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    uvm_config_db#(bit[15:0])::set(this, "env.i_agent*.seqr", "da_enable", 16'h0008);
    uvm_config_db#(int)::set(this, "env.i_agent*.seqr", "item_count", 20);
  endfunction
endclass

`endif

4.router_env.sv (派生于uvm_env)

`ifndef ROUTER_ENV__SV
`define ROUTER_ENV__SV

`include "input_agent.sv"

// Lab 3 - Task 7, Step 2
//
// To save lab time, the reset agent with its sequencer, driver and monitor has been done
// for you.  You will need to add an instance of it in the environment.
//
// Include the reset_agent.sv file
//
// ToDo
`include "reset_agent.sv"


class router_env extends uvm_env;
  input_agent i_agent;

  // Lab 3 - Task 7, Step 3
  //
  // Create an instance of reset_agent, call it r_agent
  //
  // ToDo
  reset_agent r_agent;


  `uvm_component_utils(router_env)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    i_agent = input_agent::type_id::create("i_agent", this);
    uvm_config_db #(uvm_object_wrapper)::set(this, "i_agent.seqr.main_phase", "default_sequence", packet_sequence::get_type());
    //uvm_config_db #(uvm_object_wrapper)::set(this, "i_agent.seqr.reset_phase", "default_sequence", router_input_port_reset_sequence::get_type());
    // Lab 3 - Task 7, Step 4
    //
    // Construct the r_agent object with the proxy create() method.
    //
    // ToDo
    r_agent = reset_agent::type_id::create("r_agent", this);


    // Lab 3 - Task 7, Step 5
    //
    // Configure r_agent's seqr to execute reset_sequence at reset_phase:
    // uvm_config_db #(uvm_object_wrapper)::set(this, "r_agent.seqr.reset_phase", "default_sequence", reset_sequence::get_type());
    //
    // ToDo
    uvm_config_db #(uvm_object_wrapper)::set(this, "r_agent.seqr.reset_phase", "default_sequence", reset_sequence::get_type());
    
    
  endfunction

endclass

`endif

5.input_agent.sv(派生于uvm_agent)

注1:agent包含sequencer, driver,monitor; 更高层次的组件(如env, test)应该将agent当作黑盒子,也就是说,sequencer. driver, monitor的配置应该由agent完成,更高层次的组件仅仅负责配置agent,而不需要负责agent内的子组件;

`ifndef INPUT_AGENT__SV
`define INPUT_AGENT__SV

// The files content needed by the agent must be included

`include "packet_sequence.sv"
`include "driver.sv"

typedef uvm_sequencer #(packet) packet_sequencer;

class input_agent extends uvm_agent;

  // For this lab, the input agent has been modified to have port_id and virtual interface also.
  virtual router_io sigs;          // DUT virtual interface
  int               port_id = -1;  // Agent's designated port
  packet_sequencer seqr;
  driver drv;

  // For this lab, the input agent has been modified to have port_id.
  `uvm_component_utils_begin(input_agent)
    `uvm_field_int(port_id, UVM_DEFAULT | UVM_DEC)
  `uvm_component_utils_end

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction: new

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    // For this lab, the input agent has been modified to retrieve port_id and virtual interface.
    // The agent then configures its child components to use the same port_id and virtual interface.
    uvm_config_db#(int)::get(this, "", "port_id", port_id);
    uvm_config_db#(virtual router_io)::get(this, "", "router_io", sigs);

    seqr = packet_sequencer::type_id::create("seqr", this);
    drv  = driver::type_id::create("drv", this);

    uvm_config_db#(int)::set(this, "drv", "port_id", port_id);
    uvm_config_db#(int)::set(this, "seqr", "port_id", port_id);
    uvm_config_db#(virtual router_io)::set(this, "drv", "router_io", sigs);
    uvm_config_db#(virtual router_io)::set(this, "seqr", "router_io", sigs);
  endfunction: build_phase

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    drv.seq_item_port.connect(seqr.seq_item_export);
  endfunction: connect_phase

  virtual function void start_of_simulation_phase(uvm_phase phase);
    super.start_of_simulation_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    `uvm_info("AGNTCFG", $sformatf("Using port_id of %0d", port_id), UVM_MEDIUM);
  endfunction: start_of_simulation_phase
endclass

`endif

5.1 driver.sv

`ifndef DRIVER__SV
`define DRIVER__SV

class driver extends uvm_driver #(packet);
  // Lab 4 - Task 2, Step 2 and 3
  // Create the new fields as shown below.
  //
  // virtual router_io sigs;          // DUT virtual interface
  // int               port_id = -1;  // Driver's designated port
  //
  // The intent of the port_id field is to designate the driver for driving a specific port.
  //
  // If port_id is set in the range of 0 through 15, the driver will only drive
  // the packet it gets from the sequencer through the DUT if the port_id matches the
  // packet's source address (sa) field.  If not, the packet is dropped.
  //
  // If port_id is -1 (the default), the driver will drive all packets it gets from
  // the sequencer through the DUT without checking the packet's source address.
  //
  // Example:  If port_id is 3 and req.sa is also 3,
  // (req is the packet handle that sequencer passed to the driver)
  // The driver will drive the packet through port 3 of DUT: sigs.drvClk.din[req.sa];
  //
  // Example:  If port_id is 3 and req.sa is 7,
  // The driver will drop the packet.
  //
  // Example:  If port_id is -1 and req.sa is 7,
  // The driver will drive the packet through port 7 of DUT: sigs.drvClk.din[req.sa];
  //
  // ToDo
  virtual router_io sigs;          // DUT virtual interface
  int               port_id = -1;  // Driver's designated port


  // Lab 4 - Task 2, Step 4
  //
  // Embed the port_id field in the `uvm_component_utils macro.
  // Note: You will need to change the macro to `uvm_component_utils_begin
  //       with a corresponding `uvm_component_utils_end
  //
  // ToDo
  `uvm_component_utils_begin(driver)
    `uvm_field_int(port_id, UVM_DEFAULT | UVM_DEC)
  `uvm_component_utils_end


  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction: new


  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    // Lab 4 - Task 2, Step 5
    //
    // Retrieve the port_id configuration and the virtual interface.
    //
    // uvm_config_db#(int)::get(this, "", "port_id", port_id);
    // if (!(port_id inside {-1, [0:15]})) begin
    //   `uvm_fatal("CFGERR", $sformatf("port_id must be {-1, [0:15]}, not %0d!", port_id));
    // end
    // uvm_config_db#(virtual router_io)::get(this, "", "router_io", sigs);
    // if (sigs == null) begin
    //   `uvm_fatal("CFGERR", "Interface for Driver not set");
    // end
    //
    // ToDo
    uvm_config_db#(int)::get(this, "", "port_id", port_id);
    if (!(port_id inside {-1, [0:15]})) begin
      `uvm_fatal("CFGERR", $sformatf("port_id must be {-1, [0:15]}, not %0d!", port_id));
    end
    uvm_config_db#(virtual router_io)::get(this, "", "router_io", sigs);
    if (sigs == null) begin //检测virtual interface handle;
      `uvm_fatal("CFGERR", "Interface for Driver not set");
    end


  endfunction: build_phase


  //
  // The UVM start_of_simulation phase is designed for displaying the testbench configuration
  // before any active verification operation starts.
  //
  // For the sake of lab time, the start_of_simulation method is done for you.
  //
  virtual function void start_of_simulation_phase(uvm_phase phase);
    super.start_of_simulation_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    `uvm_info("DRV_CFG", $sformatf("port_id is: %0d", port_id), UVM_MEDIUM);
  endfunction: start_of_simulation_phase


  virtual task run_phase(uvm_phase phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    forever begin
      seq_item_port.get_next_item(req);

      // Lab 4 - Task 2, Step 6
      //
      // Check port_id to see if the driver should accept or drop the packet.
      // If port_id is -1, or if port_id matches req object's sa field,
      // call send() method to drive the content of the req object through the DUT.
      // Otherwise, drop the req object without processing.  Like the following:
      //
      // if (port_id inside { -1, req.sa }) begin
      //   send(req);
      //   `uvm_info("DRV_RUN", {"\n", req.sprint()}, UVM_MEDIUM);
      // end
      //
      // ToDo
      if (port_id inside { -1, req.sa }) begin
        send(req);
        `uvm_info("DRV_RUN", {"\n", req.sprint()}, UVM_MEDIUM);
      end


      seq_item_port.item_done();
    end
  endtask: run_phase


  // Lab 4 - Task 8, Step 3
  //
  // The driver is fully responsible for asserting and de-asserting the signal set
  // that it is assigned to handle.  This includes setting the signal state at reset.
  //
  // At the pre_reset phase, the signals should be set to default values (x for logic,
  // z for wire) to emulate power-up condition.
  //
  // At the reset phase, the signals should be set to the de-asserted states.
  //
  // These two methods are done for you.
  //
  // Caution: for this lab, we are not using the port_id because this lab is still
  // just a part of initial bringup process.  There is only one agent in the
  // environment.  So, if port_id is -1 (not using port_id), then the reset phases
  // will initialized the signals for all router (DUT) ports.  In the next lab,
  // when you implement a dedicated agent for each port, the port_id will be set
  // and the reset phases will only initialize its designated port.
  //
  // For this lab, just un-comment both the pre_reset and reset phase code.
  //
  // ToDo
  //reset信号的assertion与deassertion由reset_sequence和reset_agent处理;其他控制信号,由driver的reset_phase来处理(方法1,不推荐该方法);
  virtual task pre_reset_phase(uvm_phase phase);
    super.pre_reset_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    phase.raise_objection(this);
    if (port_id == -1) begin
      sigs.drvClk.frame_n <= 'x;
      sigs.drvClk.valid_n <= 'x;
      sigs.drvClk.din <= 'x;
    end else begin
      sigs.drvClk.frame_n[port_id] <= 'x;
      sigs.drvClk.valid_n[port_id] <= 'x;
      sigs.drvClk.din[port_id] <= 'x;
    end
    phase.drop_objection(this);
  endtask: pre_reset_phase

  virtual task reset_phase(uvm_phase phase);
    super.reset_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    phase.raise_objection(this);
    if (port_id == -1) begin
      sigs.drvClk.frame_n <= '1;
      sigs.drvClk.valid_n <= '1;
      sigs.drvClk.din <= '0;
    end else begin
      sigs.drvClk.frame_n[port_id] <= '1;
      sigs.drvClk.valid_n[port_id] <= '1;
      sigs.drvClk.din[port_id] <= '0;
    end
    phase.drop_objection(this);
  endtask: reset_phase

  //
  // In the interest of lab time, all device drivers have been done for you:
  //

  virtual task send(packet tr);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    send_address(tr);
    send_pad(tr);
    send_payload(tr);
  endtask: send

  virtual task send_address(packet tr);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    sigs.drvClk.frame_n[tr.sa] <= 1'b0;
    for(int i=0; i<4; i++) begin
      sigs.drvClk.din[tr.sa] <= tr.da[i];
      @(sigs.drvClk);
    end
  endtask: send_address

  virtual task send_pad(packet tr);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    sigs.drvClk.din[tr.sa] <= 1'b1;
    sigs.drvClk.valid_n[tr.sa] <= 1'b1;
    repeat(5) @(sigs.drvClk);
  endtask: send_pad

  virtual task send_payload(packet tr);
    logic [7:0] datum;
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    while(!sigs.drvClk.busy_n[tr.sa]) @(sigs.drvClk);
    foreach(tr.payload[index]) begin
      datum = tr.payload[index];
      for(int i=0; i<$size(tr.payload, 2); i++) begin
        sigs.drvClk.din[tr.sa] <= datum[i];
        sigs.drvClk.valid_n[tr.sa] <= 1'b0;
        sigs.drvClk.frame_n[tr.sa] <= ((tr.payload.size()-1) == index) && (i==7);
        @(sigs.drvClk);
      end
    end
    sigs.drvClk.valid_n[tr.sa] <= 1'b1;
  endtask: send_payload

endclass: driver

`endif

6.reset_agent.sv(含reset_sequencer, reset_driver, reset_monitor)

`ifndef RESET_AGENT__SV
`define RESET_AGENT__SV

`include "reset_sequence.sv"

typedef class reset_driver;
typedef class reset_monitor;
typedef uvm_sequencer#(reset_tr) reset_sequencer;

class reset_agent extends uvm_agent;
  virtual router_io sigs;          // DUT virtual interface
  reset_sequencer seqr;
  reset_driver  drv;
  reset_monitor mon;
  
  `uvm_component_utils(reset_agent)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction: new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    uvm_config_db#(uvm_active_passive_enum)::get(this, "", "is_active", is_active);
    `uvm_info("RSTCFG", $sformatf("Reset agent %s setting for is_active is: %p", this.get_name(), is_active), UVM_MEDIUM);

    uvm_config_db#(virtual router_io)::get(this, "", "router_io", sigs);

    if (is_active == UVM_ACTIVE) begin
      seqr = reset_sequencer::type_id::create("seqr", this);
      drv  = reset_driver::type_id::create("drv", this);
      uvm_config_db#(virtual router_io)::set(this, "drv", "router_io", sigs);
      uvm_config_db#(virtual router_io)::set(this, "seqr", "router_io", sigs);
    end
    mon = reset_monitor::type_id::create("mon", this);
    uvm_config_db#(virtual router_io)::set(this, "mon", "router_io", sigs);
  endfunction: build_phase

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    if (is_active == UVM_ACTIVE) begin
      drv.seq_item_port.connect(seqr.seq_item_export);
    end
  endfunction: connect_phase
endclass

/*
class reset_tr extends uvm_sequence_item;
  typedef enum {ASSERT, DEASSERT} kind_e;
  rand kind_e kind;
  rand int unsigned cycles = 1;
endclass
*/

class reset_driver extends uvm_driver #(reset_tr);
  virtual router_io sigs;          // DUT virtual interface
  `uvm_component_utils(reset_driver)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction: new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    if (!uvm_config_db#(virtual router_io)::get(this, "", "router_io", sigs)) begin
      `uvm_fatal("CFGERR", "Interface for reset driver not set");
    end
  endfunction: build_phase

  virtual task run_phase(uvm_phase phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    forever begin
      seq_item_port.get_next_item(req);
      drive(req);
      seq_item_port.item_done();
    end
  endtask: run_phase
  //注1:reset_agent和reset_sequence只处理了reset信号的assertion与de-assertion;其他控制信号的处理要么通过一个单独的sequence来deassert,要么在driver的reset_phase控制;
  virtual task drive(reset_tr tr);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    if (tr.kind == reset_tr::ASSERT) begin
      sigs.reset_n = 1'b0;
      repeat(tr.cycles) @(sigs.drvClk);
    end else begin
      sigs.reset_n <= '1;
      repeat(tr.cycles) @(sigs.drvClk);
    end
  endtask: drive
endclass

class reset_monitor extends uvm_monitor;
  virtual router_io sigs;          // DUT virtual interface
  uvm_analysis_port #(reset_tr) analysis_port;
  `uvm_component_utils(reset_monitor)

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction: new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    if (!uvm_config_db#(virtual router_io)::get(this, "", "router_io", sigs)) begin
      `uvm_fatal("CFGERR", "Interface for reset monitor not set");
    end

    analysis_port = new("analysis_port", this);
  endfunction: build_phase

  virtual task run_phase(uvm_phase phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    forever begin
      reset_tr tr = reset_tr::type_id::create("tr", this);
      detect(tr);
      analysis_port.write(tr);
    end
  endtask: run_phase

  virtual task detect(reset_tr tr);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    @(sigs.reset_n);
    assert(!$isunknown(sigs.reset_n));
    if (sigs.reset_n == 1'b0) begin
      tr.kind = reset_tr::ASSERT;
    end else begin
      tr.kind = reset_tr::DEASSERT;
    end
  endtask: detect
endclass

`endif

7.packet_sequence.sv

`ifndef PACKET_SEQUENCE__SV
`define PACKET_SEQUENCE__SV

`include "packet.sv"

class packet_sequence extends uvm_sequence #(packet);

  // Lab 3 - Task 2, Step 2
  // Create the new fields as shown below.
  //
  //   int       item_count = 10;
  //   int       port_id    = -1;
  //   bit[15:0] da_enable  = '1;
  //   int       valid_da[$];
  //
  // The intent of the item_count field is to control how many packet objects
  // to create and pass on to the driver per execution of the body() task.
  //
  // The intent of the port_id field is to constrain the packet's source address.
  //
  // The lab DUT has 16 input ports needing to be tested.  Each input agent created
  // to drive a particular port will be assigned a port_id specifying which port it
  // should exercise.  Because of this, the sequence within an input agent when
  // when generating packets need to constrain the packet's source address.
  //
  // The rule for constrainint the source address shall be as follows:
  // If port_id is inside the range of {[0:15]}, then the source address shall be port_id.
  // If port_id is -1 (unconfigured), the source address shall be in the range of {[0:15]}
  // port_id outside the range of {-1, {[0:15]} is not allowed.
  //
  // The intent of the da_enable fields is to enable corresponding destination
  // addresses to be generated.  A value of 1 in a particular bit position will
  // enable the corresponding address as a valid address to generate.  A value of 0
  // prohibit the corresponding address from being generated.
  //
  // Example: if the sequence were to be configured to generate only packets
  // for destination address 3, then the da_enable need to be configured as:
  // 16'b0000_0000_0000_1000
  //
  // Note that the default value is '1, meaning that all addresses are enabled.
  //
  // To simplify the constraint coding, a corresponding set of queue, valid_da
  // is needed.  This queue is populated based on the value of da_enable.
  //
  // Example: if da_enable is 16'b0000_0011_0000_1000, then the valid_da queue
  // will populated with 3, 8 and 9.
  //
  // ToDo
  int       item_count = 10;
  int       port_id    = -1;
  bit[15:0] da_enable  = '1;
  int       valid_da[$];


  //
  // To save lab time, the `uvm_object_utils macro is filled in for you.
  //
  `uvm_object_utils_begin(packet_sequence)
    `uvm_field_int(item_count, UVM_ALL_ON)
    `uvm_field_int(port_id, UVM_ALL_ON)
    `uvm_field_int(da_enable, UVM_ALL_ON)
    `uvm_field_queue_int(valid_da, UVM_ALL_ON)
  `uvm_object_utils_end

  //
  // The valid_da queue must be populated with legal set of addresses as specified
  // by the da_enable field.  Since the first thing that the sequencer performs is
  // the randomization of its default_sequence, a good place to retreive the configuration
  // fields and populate the valid_da queue is in the pre_randomize() method.
  //
  // To simplify your code development, the code is done for you as follows:
  //
  function void pre_randomize();
    uvm_config_db#(int)::get(m_sequencer, "", "item_count", item_count);
    uvm_config_db#(int)::get(m_sequencer, "", "port_id", port_id);
    uvm_config_db#(bit[15:0])::get(m_sequencer, "", "da_enable", da_enable);
    if (!(port_id inside {-1, [0:15]})) begin
      `uvm_fatal("CFGERR", $sformatf("Illegal port_id value of %0d", port_id));
    end

    valid_da.delete();
    for (int i=0; i<16; i++)
      if (da_enable[i])
        valid_da.push_back(i);
  endfunction

  function new(string name = "packet_sequence");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  task body();
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    if (starting_phase != null)
      starting_phase.raise_objection(this);

    // Lab 3 - Task 2, Step 3
    // Instead of hard coding the number of item to be generated, replace the
    // hard-coded value 10 in the repeat() statement to use item_count.
    //
    // ToDo
    repeat(item_count) begin


      // Lab 3 - Task 2, Step 3
      //
      // As stated in the comment at the beginning of the file.  If the port_id is unconfigured (-1)
      // then the legal values for the source address shall be in the range of {[0:15]}.  If the
      // port_id is configured, then the source address shall be port_id.  This will give the test
      // the ability to test whether or not the driver drops the packet it is not configured to drive.
      //
      // For destination address, the legal values should be picked out of the valid_da array.
      //
      // Change the following `uvm_do(req) macro to:
      // `uvm_do_with(req, {if (port_id == -1) sa inside {[0:15]}; else sa == port_id; da inside valid_da;});
      //
      // ToDo
      `uvm_do_with(req, {if (port_id == -1) sa inside {[0:15]}; else sa == port_id; da inside valid_da;});


    end

    if (starting_phase != null)
      starting_phase.drop_objection(this);
 endtask

endclass

`endif

7.1packet.sv

`ifndef PACKET__SV
`define PACKET__SV

// Lab 1 - Declare the class packet that extends uvm_sequence_item
//
// ToDo
class packet extends uvm_sequence_item;

  // Lab 1 - Declare the random 4-bit sa and da fields
  //
  // ToDo
  rand bit [3:0] sa, da;

  // Lab 1 - Declare the random 8-bit payload queue
  //
  // ToDo
  rand bit[7:0] payload[$];

  `uvm_object_utils_begin(packet)
    `uvm_field_int(sa, UVM_ALL_ON | UVM_NOCOMPARE)
    `uvm_field_int(da, UVM_ALL_ON)
    `uvm_field_queue_int(payload, UVM_ALL_ON)
  `uvm_object_utils_end

  constraint valid {
    payload.size inside {[1:10]};
  }

  // Lab 1 - Create the constructor with one argument: string name="packet"
  // Lab 1 - Call super.new() with this argument
  // Lab 1 - Lastly, print a message with:
  // Lab 1 - `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  //
  // ToDo
  function new(string name = "packet");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction: new


endclass: packet
`endif

7.2 packet_da_3.sv

`ifndef PACKET_DA_3__SV
`define PACKET_DA_3__SV

class packet_da_3 extends packet;
  `uvm_object_utils(packet_da_3)

  // Lab 2 - set the constraint for destination address (da) to 3
  //
  // ToDo
  constraint da_3 {
    da == 3;
  }

  function new(string name = "packet_da_3");
    super.new(name);
   `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction
endclass

`endif

8.reset_sequence.sv

`ifndef RESET_SEQUENCE__SV
`define RESET_SEQUENCE__SV

// Reset structure is done in the same way as all other UVM component structure.
// A reset agent contains a reset sequencer, driver and monitor.
//
// The reset sequencer executes a reset sequence (this file), and passes the reset
// transaction (reset_tr) to the reset driver.  The reset driver then assert/de-assert
// the reset signal as specified in the reset transaction.
//
// Within the reset transaction class, there is a control command field called kind.
// If the kind field is ASSERT, then the driver will assert the reset signal for
// the number of clock cycles are specified in the cycles field.  Similar action
// takes place for the DEASSERT command.
//
// For example, if the reset signal need to be asserted for 2 cycles then de-asserted
// for 15 clock cycles, the potential code might look like:
//
// reset_tr tr = reset_tr::type_id::create("tr");
// tr.randomize() with {kind == ASSERT; cycles == 2;};
// tr.randomize() with {kind == DEASSERT; cycles == 15;;

class reset_tr extends uvm_sequence_item;
  typedef enum {ASSERT, DEASSERT} kind_e;
  rand kind_e kind;
  rand int unsigned cycles = 1;

  `uvm_object_utils_begin(reset_tr)
    `uvm_field_enum(kind_e, kind, UVM_ALL_ON)
    `uvm_field_int(cycles, UVM_ALL_ON)
  `uvm_object_utils_end

  function new(string name = "reset_tr");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction: new
endclass

class reset_sequence extends uvm_sequence #(reset_tr);
  `uvm_object_utils(reset_sequence)

  function new(string name = "reset_sequence");
    super.new(name);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  task body();
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);

    if (starting_phase != null)
      starting_phase.raise_objection(this);

    // Lab 4 - Task 6, Step 2
    //
    // Enter the code to assert reset for 2 cycles, followed by de-assert of reset for 15 cycles.
    //
    // ToDo
    `uvm_do_with(req, {kind == ASSERT; cycles == 2;});
    `uvm_do_with(req, {kind == DEASSERT; cycles == 15;});


    if (starting_phase != null)
      starting_phase.drop_objection(this);
   endtask

endclass

`endif

9.router_input_port_reset_sequence.sv

注1:reset_sequence和reset_agent仅仅处理了reset信号的assertion与de-assertion,其他控制信号的de-assertion可以由router_input_port_reset_sequence控制(方法2,推荐),该sequence可以在sequencer的reset_phase执行;

注2:注意get_sequencer()的使用;

注3:该sequence可以用input_agent的sequencer执行;

class router_input_port_reset_sequence extends uvm_sequence #(packet);
    virtual router_io vif;
    input             port_id=-1;
    
  `uvm_object_utils_begin(router_input_port_reset_sequence)
        `uvm_field_int(port_id, UVM_DEFAULT | UVM_DEC)
    `uvm_object_utils_end

    function new(string name="router_input_port_reset_sequence");
        super.new(name);
        `uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
        `ifdef UVM_POST_VERSION_1_1
        set_automatic_phase_objection(1);
        `endif
    endfunction

    virtual task pre_start();
        `ifdef UVM_VERSION_1_1
        if((get_parent_sequence()==null) && (starting_phase!=null)) begin
            starting_phase.raise_objection(this);
        end
        `endif

        uvm_config_db#(int)::get(get_sequencer(),"","port_id",port_id);
        if(!(port_id inside {-1,[0:15]})) begin
            `uvm_fatal("CFGERR",$sformatf("port_id must be {-1,[0:15]}, not %0d!",port_id))
        end
        uvm_config_db#(virtual router_io)::get(get_sequencer(),"","vif",vif);
        if(vif==null) begin
            `uvm_fatal("CFGERR","Interface for the Driver Reset Sequence not set")
        end
    endtask: pre_start

    `ifdef UVM_VERSION_1_1
    virtual task post_start();
        if((get_parent_sequence()==null) && (starting_phase!=null)) begin
            starting_phase.drop_objection(this);
        end
    endtask: post_start
    `endif

    virtual task body();
        if(port_id==-1) begin
            vif.frame_n='1;
            vif.valid_n='1;
            vif.din='0;
        end
        else begin
            vif.frame_n='1;
            vif.valid_n='1;
            vif.din='0;
        end
    endtask
endclass