[CU]IC仿真makefile脚本示例1

RTL_PATH    = ./rtl
TEST           = TEST_base
TB_TOP       = ./TEST.sv
UVM_HOME = ./UVM-1.2a
VERBOSITY = UVM_MEDIUM
UVM_VER    = uvm-1.2
SEED          = $(shell date +%s)

defines         = UVM_NO_DEPRECATED+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR
SOLVER       = 2


all: compile simulate

compile: *.sv $(TB_TOP)
　　vcs -sverilog -ntb_opts $(UVM_VER) -timescale="1ns/100ps" -l comp.log -debug_all +vcs+vcdpluson $(DUT) $(HARNESS_TOP) $(TB_TOP) +define+${defines}

simulate:
　　./simv -l simv.log +ntb_random_seed=$(SEED) +UVM_TESTNAME=$(TEST) +ntb_solver_mode=$(SOLVER) +UVM_VERBOSITY=$(VERBOSITY) +${plus}

//注1:在仿真时,可以通过make all TEST=testname跑指定的testcase;