[CU]reg model使用篇-reg model使用示例之uvc/seq内使用reg model

参考资料:

(1) 《Practical UVM step by step with IEEE》

(2) 《UVM实战-张强》

1. uvc内使用regmodel

//示例1:reference model中使用reg model;
class my_model extends uvm_component;
    ...
    reg_model p_rm;
    ...
endclass

task my_model::main_phase(uvm_phase phase);
    my_transaction tr;
    my_transaction new_tr;
    
    uvm_status_e   status;
    uvm_reg_data_t value; 
    super.main_phase(phase);
    p_rm.invert.read(status,value,UVM_FRONTDOOR);
    
    while(1) begin
        port.get(tr);
        new_tr=new("new_tr");
        new_tr.copy(tr);
        if(value) invert_tr(new_tr);
        ap.write(new_tr);
    end
    
endtask

function void my_env::connect_phase(uvm_phase phase);
    ...
    mdl.p_rm=this.p_rm;
    ...
endfunction

//示例2:test中使用reg_model;
class vga_lcd_reg_single_access_test_frontdoor extends vga_lcd_env_base_test;
    `uvm_component_utils(vga_lcd_reg_single_access_test_frontdoor)
    
    ral_block_vga_lcd ral_regmodel;
    uvm_status_e      status;
    uvm_reg_data_t    value_w;
    uvm_reg_data_t    value_r;
    uvm_reg           rg;

    function new(string name, uvm_component parent);
        super.new(name,parent);
    endfunction    
    
    task main_phase(uvm_phase phase);
        uvm_objection phase_done=phase.get_objection();
        phase_done.raise_objection(this);
        value_w=32'h0000_1111;

        rg=env.ral_regmodel.HTIM;
        `uvm_info(get_full_name(),"Starting Backdoor write access to HTIM", UVM_LOW)
        rg.write(status,value_w,.path(UVM_BACKDOOR));
        `uvm_info(get_full_name(),"Ending Backdoor write access to HTIM", UVM_LOW)
        
        `uvm_info(get_full_name(),"Starting Backdoor read access to HTIM", UVM_LOW)
        rg.read(status,value_r,.path(UVM_BACKDOOR));    
        `uvm_info(get_full_name(),"Ending Backdoor read access to HTIM", UVM_LOW)

        env.ral_regmodel.HTIM.write(status,value_w,.path(UVM_BACKDOOR));
        env.ral_regmodel.HTIM.read(status,value_r,.path(UVM_BACKDOOR));

        phase_done.set_drain_time(this,200);
        phase_done.drop_objection(this);
    endtask

endclass

1.1 uvc内使用reg model具体操作过程(初级版本-注意resp的处理)

1.2 uvc内使用reg model具体操作过程(通用版本-注意resp的处理)

2. sequence内使用寄存器模型

(1) 先在对应的sequencer中定义一个顶层reg_block指针,并指向base_test的reg_block对象;

(2) 在sequence中调用p_sequencer进行访问;

class case0_cfg_vseq extends uvm_sequence;
    ...
    virtual task body();
        uvm_status_e   status
        uvm_reg_data_t value;
        p_sequencer.p_rm.invert.write(status,1,UVM_FRONTDOOR);
    endtask
    ...
endclass