[CU]reg model构建篇-uvm_reg_predictor(与前门访问相关)

参考资料:

(1) Explicit Register Predictor (verificationacademy.com)

(2) 《uvm_cookbook》;

(3) SystemVerilo | UVM | 精讲RAL寄存器模型基础 (qq.com)

1.简介及uvm_reg_predictor源码

(1) uvm_predictor派生于uvm_subscriber(属于uvm_component组件类),并且是一个参数化的类,其参数类型为target bus analysis transaction;

(2) 使用uvm_predictor时,不需要对其进行派生出新类,只需要传递正确的参数类型;

(3) 使用uvm_predictor时,需要指定其uvm_reg_adapter及uvm_reg_map变量; uvm_predictor使用uvm_reg_adapter将monitor传递来的bus transaction转换成uvm_reg_item, 然后使用uvm_reg_map根据uvm_reg_item中的address信息找到对应的register,并update其内容,比如镜像值; 

(4) Predictor是保持寄存器模型“实时”复刻RTL寄存器值的关键组件。

class uvm_predict_s;
   bit addr[uvm_reg_addr_t];
   uvm_reg_item reg_item;
endclass

//------------------------------------------------------------------------------
//
// CLASS: uvm_reg_predictor
//
// Updates the register model mirror based on observed bus transactions
//
// This class converts observed bus transactions of type ~BUSTYPE~ to generic
// registers transactions, determines the register being accessed based on the
// bus address, then updates the register's mirror value with the observed bus
// data, subject to the register's access mode. See <uvm_reg::predict> for details.
//
// Memories can be large, so their accesses are not predicted.
//
//------------------------------------------------------------------------------

class uvm_reg_predictor #(type BUSTYPE=int) extends uvm_component;

  `uvm_component_param_utils(uvm_reg_predictor#(BUSTYPE))

  uvm_analysis_imp #(BUSTYPE, uvm_reg_predictor #(BUSTYPE)) bus_in;
  uvm_analysis_port #(uvm_reg_item) reg_ap;

  // Variable: map
  // The map used to convert a bus address to the corresponding register
  // or memory handle. Must be configured before the run phase.
  uvm_reg_map map;

  // The adapter used to convey the parameters of a bus operation in 
  // terms of a canonical <uvm_reg_bus_op> datum.
  // The <uvm_reg_adapter> must be configured before the run phase.
  uvm_reg_adapter adapter;

  function new (string name, uvm_component parent);
    super.new(name, parent);
    bus_in = new("bus_in", this);
    reg_ap = new("reg_ap", this);
  endfunction

  // This method is documented in uvm_object
  static string type_name = "";
  virtual function string get_type_name();
    if (type_name == "") begin
      BUSTYPE t;
      t = BUSTYPE::type_id::create("t");
      type_name = {"uvm_reg_predictor #(", t.get_type_name(), ")"};
    end
    return type_name;
  endfunction
  
  virtual function void pre_predict(uvm_reg_item rw);
  endfunction

  local uvm_predict_s m_pending[uvm_reg];

  virtual function void write(BUSTYPE tr);
     uvm_reg rg;
     uvm_reg_bus_op rw;
    if (adapter == null)
     `uvm_fatal("REG/WRITE/NULL","write: adapter handle is null") 

     // In case they forget to set byte_en
     rw.byte_en = -1;
     adapter.bus2reg(tr,rw);
     rg = map.get_reg_by_offset(rw.addr, (rw.kind == UVM_READ));

     // ToDo: Add memory look-up and call <uvm_mem::XsampleX()>

     if (rg != null) begin
       bit found;
       uvm_reg_item reg_item;
       uvm_reg_map local_map;
       uvm_reg_map_info map_info;
       uvm_predict_s predict_info;
       uvm_reg_indirect_data ireg;
       uvm_reg ir;
 
       if (!m_pending.exists(rg)) begin
         uvm_reg_item item = new;
         predict_info =new;
         item.element_kind = UVM_REG;
         item.element      = rg;
         item.path         = UVM_PREDICT;
         item.map          = map;
         item.kind         = rw.kind;
         predict_info.reg_item = item;
         m_pending[rg] = predict_info;
       end
       predict_info = m_pending[rg];
       reg_item = predict_info.reg_item;

       if (predict_info.addr.exists(rw.addr)) begin
          `uvm_error("REG_PREDICT_COLLISION",{"Collision detected for register '",
                     rg.get_full_name(),"'"})
          // TODO: what to do with subsequent collisions?
          m_pending.delete(rg);
       end

       local_map = rg.get_local_map(map,"predictor::write()");
       map_info = local_map.get_reg_map_info(rg);
       ir=($cast(ireg, rg))?ireg.get_indirect_reg():rg;

       foreach (map_info.addr[i]) begin
         if (rw.addr == map_info.addr[i]) begin
            found = 1;
           reg_item.value[0] |= rw.data << (i * map.get_n_bytes()*8);
           predict_info.addr[rw.addr] = 1;
           if (predict_info.addr.num() == map_info.addr.size()) begin
              // We've captured the entire abstract register transaction.
              uvm_predict_e predict_kind = 
                  (reg_item.kind == UVM_WRITE) ? UVM_PREDICT_WRITE : UVM_PREDICT_READ;

              if (reg_item.kind == UVM_READ &&
                  local_map.get_check_on_read() &&
                  reg_item.status != UVM_NOT_OK) begin
                 void'(rg.do_check(ir.get_mirrored_value(), reg_item.value[0], local_map));
              end
              
              pre_predict(reg_item);

              ir.XsampleX(reg_item.value[0], rw.byte_en,
                          reg_item.kind == UVM_READ, local_map);
              begin
                 uvm_reg_block blk = rg.get_parent();
                 blk.XsampleX(map_info.offset,
                              reg_item.kind == UVM_READ,
                              local_map);
              end

              rg.do_predict(reg_item, predict_kind, rw.byte_en);
              if(reg_item.kind == UVM_WRITE)
                `uvm_info("REG_PREDICT", {"Observed WRITE transaction to register ",
                         ir.get_full_name(), ": value='h",
                         $sformatf("%0h",reg_item.value[0]), " : updated value = 'h", 
                         $sformatf("%0h",ir.get())},UVM_HIGH)
              else
                `uvm_info("REG_PREDICT", {"Observed READ transaction to register ",
                         ir.get_full_name(), ": value='h",
                         $sformatf("%0h",reg_item.value[0])},UVM_HIGH)
              reg_ap.write(reg_item);
              m_pending.delete(rg);
           end
           break;
         end
       end
       if (!found)
         `uvm_error("REG_PREDICT_INTERNAL",{"Unexpected failed address lookup for register '",
                  rg.get_full_name(),"'"})
     end
     else begin
       `uvm_info("REG_PREDICT_NOT_FOR_ME",
          {"Observed transaction does not target a register: ",
            $sformatf("%p",tr)},UVM_FULL)
     end
  endfunction

  
  // Function: check_phase
  // Checks that no pending register transactions are still queued.
  virtual function void check_phase(uvm_phase phase);
    ...
  endfunction

endclass

2. 前门读操作提供返回值的两种方式

2.1 auto_predict功能(没有使用monitor的implict prediction)

(1) rm.default_map.set_auto_predict(1);

(2) 能够这样操作的原因在于: 由于总线的特殊性,bus_driver在驱动总线进行读操作时,它也能顺便获取要读的数值,如果它将此值放入从bus_sequencer获得的bus_transaction中,那么bus_transaction中就会有读取的值,此值经过adapter的bus2reg函数的传递,最终被寄存器模型获取;

2.2 依靠monitor与uvm_reg_predictor的非auto_predict功能(使用monitor的explict prediction)

(1) monitor将从总线上收集到的transaction交给寄存器模型,后者更新相应寄存器的值.

3. auto_predict读操作返回值详细分析

(1) 由于总线的特殊性, bus_driver在驱动总线进行读操作时,也能顺便获取要读的数值; 如果将该值放入从bus_sequencer获得的bus_transaction中,那么bus_transaction中就会有读取的值; 此值经过adapter的bus2reg函数的传递,最终被寄存器模型获取，寄存器模型会更新寄存器的镜像值和期望值,这就是寄存器模型的auto predict功能, 如下图虚线所示;

(2) auto predict功能的具体应用

注1:寄存器模型的前门访问操作最终都将由uvm_reg_map完成,因此在connect_phase中,需要将转换器uvm_reg_adapter和bus_sequencer通过set_sequencer函数告知reg_model的default_map,并将default_map设置为自动预测状态;

//示例1
class base_test extends uvm_test;
    my_env     env;
    my_vsqr    vsqr;
    reg_model  rm;
    my_adapter reg_sqr_adapter
    ...
endclass

function void base_test::build_phase(uvm_phase phase);
    super.build_phase(phase);
    env=my_env::type_id::create("env",this);
    vsqr=my_vsqr::type_id::create("vsqr",this);

    rm=reg_model::type_id::create("rm",this);
    rm.configure(null,"");
    rm.build();
    rm.lock_model();
    rm.reset();

    reg_sqr_adapter=new("reg_sqr_adapter");
    env.p_rm=this.rm;    
endfunction

function void base_test::connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    vsqr.p_my_sqr=env.i_agt.sqr;
    vsqr.p_bus_sqr=env.bus_agt.sqr;
    vsqr.p_rm=this.rm;

    rm.default_map.set_sequencer(env.bus_agt.sqr,reg_sqr_adapter);
    rm.default_map.set_auto_predict(1);

endfunction

4. 依赖monitor与uvm_reg_predictor的读操作返回值

 (1) 该方法的原理如下图中的右图所示; 使用这种方式更新数据,需要设置reg_predictor的adapter和map(只有设置了map,才能将predictor和寄存器模型关联在一起),并且需要将reg_predictor和bus_agt的ap口连接在一起;

(2) 当总线上可能有众多设备发起读写操作时,有一个monitor是非常有必要的; 

(3) 使用示例

注1:在该代码示例中,存在着两条更新寄存器模型的路径: 一是左侧虚线所示的自动预测路径,二是经由predictor的途径; 如果要彻底关掉自动预测的路径,需要set_auto_predict(0);

//示例1
class base_test extends uvm_test;
    ...
    reg_model  rm;
    my_adapter reg_sqr_adapter;
    //adapter for uvm_reg_predictor;
    my_adapter mon_reg_adapter;
    uvm_reg_predictor #(bus_transaction) reg_predictor;
    ...
endclass

function void base_test::build_phase(uvm_phase phase);
    ...
    rm=reg_model::type_id::create("rm",this);
    rm.configure(null,"");
    rm.build();
    rm.lock_model();
    rm.reset();

    reg_sqr_adapter=new("reg_sqr_adapter");
    mon_reg_adapter=new("mon_reg_adapter");
    reg_predictor=new("reg_predictor",this);
    env.p_rm=this.rm;    
endfunction

function void base_test::connect_phase(uvm_phase phase);
    ...
    rm.default_map.set_sequencer(env.bus_agt.sqr,reg_sqr_adapter);
    //读操作返回值方式1:auto predict;
    rm.default_map.set_auto_predict(1);
    //读操作返回值方式2:monitor & uvm_reg_predictor;
    reg_predictor.map=rm.default_map;
    reg_predictor.adapter=mon_reg_adapter;
    env.bus_agt.ap.connect(reg_predictor.bus_in);
endfunction

//示例2
class environment extends uvm_env;
    typedef uvm_reg_predictor #(master_data) mreg_predictor;
    mreg_predictor mreg_predict;

    virtual function void build_phase(uvm_phase phase);
        mreg_predict=mreg_predictor::type_id::create("mreg_predict",this);
    endfunction
    
    virtual function void connect_phase(uvm_phase phase);
        mreg_predict.map=regmodel.get_default_map();    
        mreg_predict.adapter=adapter;
        regmodel.default_map.set_auto_predict(0);
        m_agent.analysis_port.connect(mreg_predict.bus_in);
    endfunction
endclass

5. 两种读操作返回值方法的区别

(1) 当总线上只有一个主设备时,两种读操作返回值方法等价; 如果有多个主设备,自动预测的方法会漏掉某些transaction;

(2) Explicit Prediction相对于Implicit Prediction，除了监视通过寄存器模型API对寄存器的访问操作，还可以覆盖到其他测试序列（sequence）通过总线对寄存器的直接访问，这一点会使它更加通用。