[CU]reg model构建篇-uvm_reg_field

资料来源

(1) 《UVM cookbook》

前言

(1) 按照单位由小到大依次罗列,分别为uvm_reg_field->uvm_reg,uvm_mem,uvm_reg_file,uvm_reg_map->uvm_reg_adapter,uvm_reg_block, uvm_reg_predictor;

1. uvm_reg_field概念

(1) uvm_reg_field是寄存器模型的最小单位,在uvm_reg的build函数内实例化,和DUT中每个register里的field对应;

 

2. uvm_reg_field源码

`ifndef UVM_REG_ADDR_WIDTH
    //可以通过改变这个宏的值来改变register model所能表示的最大寄存器的值;
    `define UVM_REG_ADDR_WIDTH 64
`endif

`ifndef UVM_REG_DATA_WIDTH
 `define UVM_REG_DATA_WIDTH 64
`endif

typedef bit unsigned[`UVM_REG_DATA_WIDTH-1:0] uvm_reg_data_t;

class uvm_reg_field extends uvm_object;

   //注意value的类型是rand,表示可以进行随机化;
   rand  uvm_reg_data_t  value; // Mirrored after randomize()

   local uvm_reg_data_t  m_mirrored; // What we think is in the HW
   local uvm_reg_data_t  m_desired;  // Mirrored after set()

   //下面这组变量在调用uvm_reg_field的configure函数时,进行初始化操作;
   local string          m_access; //表示reg_field的存储特性,如RW,RO等;
   local uvm_reg         m_parent; //表示reg_field所在uvm_reg的指针;
   local int unsigned    m_lsb;    //表示reg_field最低位在uvm_reg中的位置;
   local int unsigned    m_size;   //表示reg_field占据了几个bit;
   local bit             m_volatile; //表示reg_field的volatile特性;
   //表示reg_field复位后的值,m_reset是一个联合数组,表示reg_field可以有多个复位值,如硬复位,软复位等;
   local uvm_reg_data_t  m_reset[string];
   local bit             m_written;
   local bit             m_read_in_progress;
   local bit             m_write_in_progress;
   local string          m_fname;
   local int             m_lineno;
   local int             m_cover_on;
   local bit             m_individually_accessible;
   local uvm_check_e     m_check;
     ...
endclass

//示例
class my_fld_type extends uvm_reg_field;
    `uvm_object_utils(my_fld_type)
    
    function new(string name="my_fld_type");
        super.new(name);
    endfunction

    constraint valid { value inside {0,1,2,4,8,16,32};};
endclass

3. uvm_reg_field的configure函数

(1) configure函数首先对一些成员变量进行赋值;

(2) 在调用m_parent(uvm_reg)的add_field函数时,函数内部会检测register是否已经被lock住了; 如果被lock住,该reg中就不能再加入任何field(一般的,当整个register model建立完成后,会在最顶层的uvm_reg_block调用lock相关函数,将整个模型锁起来);

(3)调用m_parent的add_field函数的效果是将该field加入到uvm_reg的m_fields数组中(这部分的源代码不错);

(4) uvm_reg_field的例化以及configure函数的调用均在uvm_reg的build函数内实现;

function void uvm_reg_field::configure(uvm_reg        parent,
                                       int unsigned   size,
                                       int unsigned   lsb_pos,
                                       string         access,
                                       bit            volatile,
                                       uvm_reg_data_t reset,
                                       bit            has_reset,
                                       bit            is_rand,
                                       bit            individually_accessible); 
   m_parent = parent;
   if (size == 0) begin
      `uvm_error("RegModel",
         $sformatf("Field \"%s\" cannot have 0 bits", get_full_name()));
      size = 1;
   end

   m_size      = size;
   m_volatile  = volatile;
   m_access    = access.toupper();
   m_lsb       = lsb_pos;
   m_cover_on  = UVM_NO_COVERAGE;
   m_written   = 0;
   m_check     = volatile ? UVM_NO_CHECK : UVM_CHECK;
   m_individually_accessible = individually_accessible;

   if (has_reset)
      set_reset(reset);
   else
      uvm_resource_db#(bit)::set({"REG::", get_full_name()},
                                 "NO_REG_HW_RESET_TEST", 1);

 m_parent.add_field(this);

   if (!m_policy_names.exists(m_access)) begin
      `uvm_error("RegModel", {"Access policy '",access,
       "' for field '",get_full_name(),"' is not defined. Setting to RW"})
      m_access = "RW";
   end

   if (size > m_max_size)
      m_max_size = size;
   
   // Ignore is_rand if the field is known not to be writeable
   // i.e. not "RW", "WRC", "WRS", "WO", "W1", "WO1"
   case (access)
    "RO", "RC", "RS", "WC", "WS",
      "W1C", "W1S", "W1T", "W0C", "W0S", "W0T",
      "W1SRC", "W1CRS", "W0SRC", "W0CRS", "WSRC", "WCRS",
      "WOC", "WOS": is_rand = 0;
   endcase

   if (!is_rand)
     value.rand_mode(0);

   m_field_registry[get_full_name()] = this;
endfunction: configure

关于uvm_reg_field configure函数输入参数的含义详见<<UVM实战>>参考资料;

参数1含义:该uvm_reg_field的父辈,即该域位于哪个寄存器中,传递为this;

参数2含义:该uvm_reg_field的宽度;

参数3含义:该uvm_reg_field最低位在该寄存器中的位置,从0开始计数;

参数4含义:该uvm_reg_field的存取方式,如RO,RW,RC,RS等25中存取方式,用户可自定义存取方式;

注1: RW的测试,先写后读,写全0,全1,全a,全5;

注2: RO的测试,先写一个非零值,再读,读出值是0,测不可写;

注3: WO的测试,先写一个非零值,再读,读出值是0;

注4: RC的测试,寄存器有一个非零值,读出,会返回非零值(???),再读,会返回0;

参数5含义:表明是否为易失的;

参数6含义:表明该uvm_reg_field上电复位后的默认值;

参数7含义:表明该uvm_reg_field是否有上电复位;

参数8含义:表明该域是否可以随机化;

参数9含义:表明该域是否可以单独存取;

4. uvm_reg_field的其他操作

 (1) 当通过uvm_reg_field::read()或uvm_reg_field::write()进行register field的读写操作时,实际发生什么取决于多种因素,可能只是该register field被读写,也可能是包含该register field的整个register被读写;