verilog仿真信号文本抓取 

module textinsert #(
    parameter DW = 32,
    parameter NAME = "test.txt"
)
(
    input logic          clk  ,
    input logic          en   ,
    input logic          stop ,
    input logic [DW-1:0] data  
);

integer fd;

initial begin
    fd = $fopen(NAME,"w");
    while(!stop)begin
        @(posedge clk)begin
            if(en) $fdisplay(fd,"%h",data);
        end
    end
    $fclose(fd);
end

endmodule
posted @ 2023-12-19 11:25  AdriftCore  阅读(71)  评论(0)  编辑  收藏  举报