memory bist lib 

 1 model NVIC_REG6T_1024x32(resetb,margin,clk,en,we,addr,d,q)
 2 (
 3      bist_definition(
 4            clock     clk    high;
 5            chip_enable   en    low;
 6            write_enable   we   high;
 7            data_in      d(array=31:0;);
 8            data_out    q(array=31:0;);
 9            address      addr(array=9:0;);
10 
11 
12           dont_touch  margin(array=1:0;)high;
13           dont_touch   resetb low;
14 
15           tech = smic11;
16           vendor = mentor;
17           version="1.0";
18           message= "synchrous single port sram";
19           
20           address_size = 10;
21           min_address = 0;
22           max_address = 32;
23          
24           read_write_port(
25                read_cycle(
26                    change addr;
27                    wait;
28                    wait;
29                    expect q;
30                    wait; 
31                 )
32                write_cycle(
33                     change addr;
34                     change d;
35                     wait ;
36                     assert we;
37                     wait;
38                     wait;  
39                   )
40 
41            )
42   
43       )
44 
45 )

写model中，write/read timing 紧凑，很重要，比较难。有的memory model 含有sw(subword) write enable项，tessent工具可以很好的支持，另外UDA可以实现sw部分为0/1。

以上是SRAM 的model，下面是ROM 的model 模板

 1 model NVIC_ROM_1024x32(resetb,margin,clk,en,addr,q)
 2 (
 3     bist_definition(
 4             clock  clk  high ;
 5             chip_enable en low;
 6             data_out      q(array=31:0;);
 7             address    addr(array=9:0;);
 8          
 9              dont_touch       margin high;
10              dont_touch       resetb  low;
11 
12              tech = smic11;
13              vendor = mentor;
14              version = "1.0";
15              message = "synchronous single port sram";
16               
17              address_size = 10;
18              min_address = 0;
19              max_address = 1023;
20              data_size = 32;
21 
22               read_port(
23                    read_cycle(
24                        change addr;
25                        wait;
26                        expect q;
27                        wait;
28                     )
29                )
30 
31       )
32 
33 
34 
35 
36 
37 
38 
39 
40 )

 

posted @ 2016-01-20 21:18  CHIPER  阅读(958)  评论(1)  编辑  收藏  举报