AHB2reg接口转换 

 1 assign mcu_xxx_addr = (rd_after_wr_reg || reg_valid_write_trans) ?
 2                  haddr_reg[ADDR_WIDTH+1:2] : haddr[ADDR_WIDTH+1:2];
 3 assign mcu_xx_rd_n = rd_after_wr ?  1'b1 : rd_after_wr_reg ? 1'b0 :       ~valid_read_trans;
 4 assign mcu_xxx_wr_n = ~(hready && reg_valid_write_trans);
 5 assign mcu_xxx_dat = hwdata;
 6 assign rd_after_wr = hready && valid_read_trans && reg_valid_write_trans;
 7 ----------------------------------------------------------------------------
 8 assign hsize_error = BYTE_MASK ? ((hsize = SZ_DWORD) ||hsize[2]) :
 9           (hsize != SZ_WORD);
10 assign valid_trans = hready && hsel && htrans[1] && !hsize_error;
11 assign error_trans = hready && hsel && htrans[1] && hsieze_error;
12 assign valid_read_trans = valid_trans && !hwrite;
13 assign  valid_write_trans = valid_trans && hwrite;
14  
15 
16 -------------------------------------------------------------------------------
17 always@(posedge hclk or negedge hresetn) 
18    begin 
19         if(~hresetn)
20           begin
21               haddr_reg <=0;
22               htrans_reg <= 0;
23               hwrite_reg <= 0;
24               hsize_reg <= 0;
25               reg_valid_read_trans <=0;
26               reg_valid_write_trans  <= 0;
27            end
28          else
29             begin
30                if(hready)
31                    begin 
32                       haddr_reg <= haddr;
33                       htrans_reg <= htrans;
34                       hwrite_reg <= hwrite;
35                       hsize_reg <= hsize;
36                       reg_valid_read_trans <=valid_read_trans;
37                       reg_valid_write_trans  <= valid_write_trans;
38                     end
39               end
40          end
41                        
42  
43 
44 --------------------------------------------------------------------------------
45   always@(*)
46      begin
47          if(hready && reg_valid_write_trans)
48             begin
49                 mcu_xxx_wr_en = 4'b0;
50                 case(hsize_reg)
51                     SZ_BYTE:
52                       case(haddr_reg[1:0])
53                          2'b00: mcu_xxx_wr_en[0] = 1'b1;
54                          2''b01: mcu_xxx_wr_en[1] = 1'b1;
55                          2'b10: mcu_xxxx_wr_en[2] = 1'b1;
56                          2'b11: mcu_xxx_wr_en [3]  = 1'b1;
57                       endcase
58  
59                    SZ_HALF:
60                        case(haddr_reg[1])
61                            1'b0 : mcu_xxx_wr_en[1:0] = 2'b11;
62                            1'b1 :  mcu_xxx_wr_en [3:2] = 2'b11;
63                        endcase
64  
65                    SZ_WORD:
66                         mcu_xxx_wr_en = 4'b1111;
67  
68                     default:
69                         mcu_xxx_wr_en = 4'b1111;
70  
71                     endcase
72                end
73              else
74                  begin 
75                      mcu_xxx_wr_en = 4'b0;
76                   end
77                end

 

 本code主要实现AHB时序转MEMORY接口时序：

由于，AHB总线读写都是2拍，在ready信号拉高时表示数据读写完成，并且下一拍地址传到总线上。

          memory 读写时序，读时序也是2拍，所以可以直接使用AMB总线的读使能。但写时序不一样。对于memory读使能有效时，可以立即把写数据送到写总线上，不像AHB写时必须2拍。所以写时，需要把AHB的HWRITE相关信号寄存一拍。

          特别是，当先写后读时，要注意时序转换。即code中rd_after_wr。目前理解的是，整体把读使能也寄存了一拍。

posted @ 2015-02-04 20:09  CHIPER  阅读(532)  评论(0)  编辑  收藏  举报