verilog behavioral modeling --loop statement

1.forever

2.repeat

3.while

4.for

The for statement accomplishes the same results as the following pseudo-code that is based on the while loop:

 

  begin

      initial_assignment;

      while(condition)begin

          statement;

          step_assignment;

      end

  end

 

  for(initial_assignment; condition; step_assignment)

    statement;