Image Sub-pixel interpolation by Verilog
bilinear interpolation
--------------------------------------------------------
input
a0 a1
b0 b1
--------------------------------------------------------
- t1 = a0*(1-dx) + a1*dx
- t2 = b0*(1-dx) + b1*dx
- c = t1*(1-dy) + t2*dy
c is the output
-------------------------------------------------------
`define _DEBUG
module sub_pixel(clk
, rst_n
, a_en
, a0
, a1
, b0
, b1
, dx
, dy
, c
, c_en
`ifdef _DEBUG
, _sum_a0_s2
, _sum_a1_s2
, _sum_b0_s2
, _sum_b1_s2
`endif
);
parameter SHIFT_BITS = 4'd10;
localparam SCALE = 32'd1<<SHIFT_BITS;
input clk, rst_n, a_en;
input [7:0]a0, a1, b0, b1;
input [(SHIFT_BITS-1):0]dx, dy;
output [7:0]c;
output c_en;
`ifdef _DEBUG
output [31:0]_sum_a0_s2;
output [31:0]_sum_a1_s2;
output [31:0]_sum_b0_s2;
output [31:0]_sum_b1_s2;
`endif
//////////////////////////////////////////
//Step 1
reg [7:0]a0_s1, a1_s1, b0_s1, b1_s1;
reg [31:0]_dx_s1, _dy_s1, _1_dx_s1, _1_dy_s1;
reg a_en_s1;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
_dx_s1 <= 32'd0;
_dy_s1 <= 32'd0;
_1_dx_s1 <= 32'd0;
_1_dy_s1 <= 32'd0;
a0_s1 <= 8'd0;
a1_s1 <= 8'd0;
b0_s1 <= 8'd0;
b1_s1 <= 8'd0;
a_en_s1 <= 1'd0;
end
else
begin
_dx_s1 <= dx;
_dy_s1 <= dy;
_1_dx_s1 <= SCALE - dx;
_1_dy_s1 <= SCALE - dy;
a0_s1 <= a0;
a1_s1 <= a1;
b0_s1 <= b0;
b1_s1 <= b1;
a_en_s1 <= a_en;
end
end
//////////////////////////////////////////
//Step 2
reg a_en_s2 = 1'd0;
reg [31:0]_dy_s2, _1_dy_s2;
reg [31:0]sum_a0_s2 = 32'd0;
reg [31:0]sum_a1_s2 = 32'd0;
reg [31:0]sum_b0_s2 = 32'd0;
reg [31:0]sum_b1_s2 = 32'd0;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
a_en_s2 <= 1'd0;
_dy_s2 <= 32'd0;
_1_dy_s2 <= 32'd0;
sum_a0_s2 <= 32'd0;
sum_a1_s2 <= 32'd0;
sum_b0_s2 <= 32'd0;
sum_b1_s2 <= 32'd0;
end
else
begin
a_en_s2 <= a_en_s1;
_dy_s2 <= _dy_s1;
_1_dy_s2 <= _1_dy_s1;
sum_a0_s2 <= a0_s1*_1_dx_s1;
sum_a1_s2 <= a1_s1*_dx_s1;
sum_b0_s2 <= b0_s1*_1_dx_s1;
sum_b1_s2 <= b1_s1*_dx_s1;
end
end
//////////////////////////////////////////
//Step 3
reg a_en_s3 = 1'd0;
reg [31:0]_dy_s3, _1_dy_s3;
reg [31:0]sum_a_s3 = 32'd0;
reg [31:0]sum_b_s3 = 32'd0;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
a_en_s3 <= 1'd0;
_dy_s3 <= 32'd0;
_1_dy_s3 <= 32'd0;
sum_a_s3 <= 32'd0;
sum_b_s3 <= 32'd0;
end
else
begin
a_en_s3 <= a_en_s2;
_dy_s3 <= _dy_s2;
_1_dy_s3 <= _1_dy_s2;
sum_a_s3 <= sum_a0_s2 + sum_a1_s2;
sum_b_s3 <= sum_b0_s2 + sum_b1_s2;
end
end
//////////////////////////////////////////
//Step 4
reg a_en_s4 = 1'd0;
reg [31:0]sum_a_s4 = 32'd0;
reg [31:0]sum_b_s4 = 32'd0;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
a_en_s4 <= 1'd0;
sum_a_s4 <= 32'd0;
sum_b_s4 <= 32'd0;
end
else
begin
a_en_s4 <= a_en_s3;
sum_a_s4 <= sum_a_s3[31:(SHIFT_BITS-1)]*_1_dy_s3;
sum_b_s4 <= sum_b_s3[31:(SHIFT_BITS-1)]*_dy_s3;
end
end
//////////////////////////////////////////
//Step 5
reg a_en_s5 = 1'd0;
reg [31:0]sum_s5 = 1'd0;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
a_en_s5 <= 1'd0;
sum_s5 <= 1'd0;
end
else
begin
a_en_s5 <= a_en_s4;
sum_s5 <= sum_a_s4 + sum_b_s4;
end
end
assign c = sum_s5[(SHIFT_BITS+8):(SHIFT_BITS+1)];
assign c_en = a_en_s5;
`ifdef _DEBUG
assign _sum_a0_s2 = sum_a0_s2;
assign _sum_a1_s2 = sum_a1_s2;
assign _sum_b0_s2 = sum_b0_s2;
assign _sum_b1_s2 = sum_b1_s2;
`endif
endmodule
----------------------------------------------------------------------------
////////////////TEST BENCH/////////////////////////
////////////////////////////////////////////////////////
`define _DEBUG
`timescale 1 ns/ 1 ns
module sub_pixel_vlg_tst();
parameter SHIFT_BITS = 4'd10;
localparam SCALE = 32'd1<<SHIFT_BITS;
// test vector input registers
reg [7:0] a0;
reg [7:0] a1;
reg a_en;
reg [7:0] b0;
reg [7:0] b1;
reg clk;
reg [9:0] dx;
reg [9:0] dy;
reg rst_n;
// wires
wire [7:0]c;
wire c_en;
`ifdef _DEBUG
wire [31:0]_sum_a0_s2;
wire [31:0]_sum_a1_s2;
wire [31:0]_sum_b0_s2;
wire [31:0]_sum_b1_s2;
`endif
// assign statements (if any)
sub_pixel i1 (
.clk(clk)
, .rst_n(rst_n)
, .a_en(a_en)
, .a0(a0)
, .a1(a1)
, .b0(b0)
, .b1(b1)
, .dx(dx)
, .dy(dy)
, .c(c)
, .c_en(c_en)
`ifdef _DEBUG
, ._sum_a0_s2(_sum_a0_s2)
, ._sum_a1_s2(_sum_a1_s2)
, ._sum_b0_s2(_sum_b0_s2)
, ._sum_b1_s2(_sum_b1_s2)
`endif
);
initial
begin
clk = 0;
forever #5 clk <= ~clk;
end
initial
begin
rst_n <= 0;
a_en <= 0;
#(5 + 100) rst_n <= 1;
@(posedge clk)
begin
a_en <= 1; a0 <= 4; a1 <= 6; b0 <= 8; b1 <= 10; dx <= SCALE/2; dy <= SCALE/2;
end
@(posedge clk)
begin
a_en <= 1; a0 <= 40; a1 <= 60; b0 <= 80; b1 <= 100; dx <= SCALE/2; dy <= SCALE/2;
end
@(posedge clk)
begin
a_en <= 1; a0 <= 40; a1 <= 60; b0 <= 80; b1 <= 100; dx <= SCALE/4; dy <= SCALE/4;
end
@(posedge clk)
begin
a_en <= 1; a0 <= 40; a1 <= 60; b0 <= 80; b1 <= 100; dx <= SCALE/10; dy <= SCALE/10;
end
@(posedge clk)
begin
a_en <= 1; a0 <= 40; a1 <= 60; b0 <= 80; b1 <= 100; dx <= SCALE - SCALE/10; dy <= SCALE - SCALE/10;
end
@(posedge clk)
begin
a_en = 0;
end
#5000 $stop;
end
endmodule
