固定脉冲宽度信号生成---基于定时器和边沿检测
1 //-------------------------------------------------------------------------------------------------- 2 // fixed by chensimin 3 //-------------------------------------------------------------------------------------------------- 4 wire decoder_0_rst; 5 wire decoder_0_hpd; 6 assign decoder_0_rst = decoder_0_control_0[ `BIT_DECODER_CONTROL_0_RESET ]; 7 assign decoder_0_hpd = decoder_0_control_0[ `BIT_DECODER_CONTROL_0_HPD ]; 8 9 //-------------------------------------------------------------------------------------------------- 10 // rising_phd edge hpd信号同步与上升沿检测 11 12 reg decoder_0_hpd_delay; 13 reg decoder_0_hpd_delay_1; 14 reg decoder_0_hpd_delay_2; 15 wire rising_phd; 16 17 always @(posedge clk_25m or posedge bus_reset) 18 begin 19 if(bus_reset) 20 begin 21 decoder_0_hpd_delay <= 1'b0; 22 decoder_0_hpd_delay_1 <= 1'b0; 23 decoder_0_hpd_delay_2 <= 1'b0; 24 end 25 26 else 27 begin 28 decoder_0_hpd_delay <= decoder_0_hpd; 29 decoder_0_hpd_delay_1 <= decoder_0_hpd_delay; 30 decoder_0_hpd_delay_2 <= decoder_0_hpd_delay_1; 31 end 32 end 33 34 assign rising_phd = (!decoder_0_hpd_delay_2) && decoder_0_hpd_delay_1; 35 36 //-------------------------------------------------------------------------------------------------- 37 38 //rising_rst 复位信号同步与上升沿检测 39 40 reg decoder_0_rst_delay; 41 reg decoder_0_rst_delay_1; 42 reg decoder_0_rst_delay_2; 43 wire rising_rst; 44 45 always @(posedge clk_25m or posedge bus_reset) 46 begin 47 if(bus_reset) 48 begin 49 decoder_0_rst_delay <= 1'b0; 50 decoder_0_rst_delay_1 <= 1'b0; 51 decoder_0_rst_delay_2 <= 1'b0; 52 end 53 54 else 55 begin 56 decoder_0_rst_delay <= decoder_0_rst; 57 decoder_0_rst_delay_1 <= decoder_0_rst_delay; 58 decoder_0_rst_delay_2 <= decoder_0_rst_delay_1; 59 end 60 end 61 62 assign rising_rst = (!decoder_0_rst_delay_2) && decoder_0_rst_delay_1; 63 64 //-------------------------------------------------------------------------------------------------- 65 66 // get 1us 1微妙计数器，计时器开机复位，然后便开始计数，当接收到rising_phd信号后，计数器清零，作为有效计数的起始点 67 68 reg get_time_1us ; 69 reg [31:0] m ; 70 always @(posedge clk_25m or posedge bus_reset ) 71 begin 72 if(bus_reset) 73 begin 74 get_time_1us <= 1'b0; 75 m <= 0; 76 end 77 else if(rising_phd) 78 begin 79 get_time_1us <= 1'b0; 80 m <= 0; 81 end 82 else if(m == 24) 83 begin 84 get_time_1us <= 1'b1; 85 m <= 0; 86 end 87 else 88 begin 89 get_time_1us <= 1'b0; 90 m <= m + 1'b1; 91 end 92 end 93 94 //-------------------------------------------------------------------------------------------------- 95 96 // output hdmi_hpd 固定脉宽hpd信号生成模块，hpd信号开机复位并保持低电平，当接收到rising_phd信号触发后 97 // hpd信号拉高，并清空计数器，此时作为hpd高电平信号的起点，当k=1000000时候，hpd信号拉低，计数器清零。 98 99 reg hdmi_hpd ; 100 reg [31:0] k ; 101 102 always @(posedge clk_25m or posedge bus_reset ) 103 begin 104 if(bus_reset) 105 begin 106 hdmi_hpd <= 1'b0; 107 k <= 0; 108 end 109 else if(rising_phd) 110 begin 111 hdmi_hpd <= 1'b1; 112 k <= 0; 113 end 114 else if(k==1000000) 115 begin 116 hdmi_hpd <= 1'b0; 117 k <= 0; 118 end 119 else if(get_time_1us) 120 k <= k + 1; 121 end 122 123 //-------------------------------------------------------------------------------------------------- 124 125 // get 1us 1微妙计数器，用于另外一个信号的控制 126 127 reg get_time_1us_1 ; 128 reg [31:0] i ; 129 always @(posedge clk_25m or posedge bus_reset ) 130 begin 131 if(bus_reset) 132 begin 133 get_time_1us_1 <= 1'b0; 134 i <= 0; 135 end 136 else if(rising_rst) 137 begin 138 get_time_1us_1 <= 1'b0; 139 i <= 0; 140 end 141 else if(i == 24) 142 begin 143 get_time_1us_1 <= 1'b1; 144 i <= 0; 145 end 146 else 147 begin 148 get_time_1us_1 <= 1'b0; 149 i <= i + 1'b1; 150 end 151 end 152 153 //-------------------------------------------------------------------------------------------------- 154 155 // hdmi_reset 复位信号的产生，控制复位信号的宽度 156 157 reg [31:0] j ; 158 159 always @(posedge clk_25m or posedge bus_reset) 160 begin 161 if(bus_reset) 162 begin 163 hdmi_reset <= 1'b0; 164 j <= 0; 165 end 166 else if(rising_rst) 167 begin 168 hdmi_reset <= 1'b0; 169 j <= 0; 170 end 171 else if(j==8000) 172 begin 173 hdmi_reset <= 1'b1; 174 j <= 0; 175 end 176 else if(get_time_1us_1) 177 j <= j + 1; 178 end
