关于AXI_Quad_SPI的寄存器配置
1.核初始化配置
首先是：
40:0000_000A
1C:8000_0000
28:0000_0004
2.命令与dummy_data
60:000001E6
60:00000186
68:{24'h000000,cmd}
68:{24'h000000,add0}
68:{24'h000000,add1}
68:{24'h000000,add2}
68:{24'h000000,data1}
68:{24'h000000,data2}
68:{24'h000000,data3}
68:{24'h000000,DUMMY_DATA}
68:{24'h000000,DUMMY_DATA}
68:{24'h000000,DUMMY_DATA}
68:{24'h000000,DUMMY_DATA}
68:{24'h000000,DUMMY_DATA}
68:{24'h000000,DUMMY_DATA}
68:{24'h000000,DUMMY_DATA}
68:{24'h000000,DUMMY_DATA}
70:00000000
60:00000086
20:00000004
70:FFFFFFFF
60:00000186
AXI_Quad_SPI核在使用中碰到的问题：
对IP核进行初始化后，执行的第一个命令无效，第二个命令才能正常执行，如果开机第一个命令需要执行写使能命令，即需要把写使能命令执行两边，第二个才生效，第三个，第四个...均能正常执行。这个问题与SPI的clk 调用了startup primitive这一源语有关。
1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: chensimin 5 // 6 // Create Date: 2018/02/01 10:32:30 7 // Design Name: 8 // Module Name: top 9 // Project Name: 10 // Target Devices: 11 // Tool Versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 22 23 module top( 24 25 input clk_27m_in, 26 inout [3:0]spi_dq, 27 inout spi_ss 28 29 ); 30 31 //-------------------------------------------------------------- 32 wire clk_100M; 33 clk_wiz_0 U2( 34 .clk_out1(clk_100M), 35 .clk_in1(clk_27m_in) 36 ); 37 38 //-------------------------------------------------------------- 39 wire rst; 40 //wire start_write; 41 wire start_core_init; 42 wire finish_core_init; 43 wire start_core_write; 44 wire wait_core_int; 45 wire finish_core_write; 46 wire start_read; 47 wire [31:0]axi_araddr; 48 wire core_init_en; 49 wire core_write_en; 50 wire [7:0]cmd; 51 wire [7:0]add0; 52 wire [7:0]add1; 53 wire [7:0]add2; 54 wire [7:0]data1; 55 wire [7:0]data2; 56 wire [7:0]data3; 57 vio_0 U3 ( 58 .clk(clk_100M), // input wire clk 59 .probe_out0(rst), // output wire [0 : 0] probe_out0 60 .probe_out1(start_core_init), // output wire [0 : 0] probe_out1 61 .probe_out2(start_read), // output wire [0 : 0] probe_out2 62 .probe_out3(axi_araddr), // output wire [31 : 0] probe_out3 63 .probe_out4(core_init_en), // output wire [0 : 0] probe_out4 64 .probe_out5(core_write_en), // output wire [0 : 0] probe_out5 65 .probe_out6(cmd), // output wire [7 : 0] probe_out6 66 .probe_out7(add0), // output wire [7 : 0] probe_out7 67 .probe_out8(add1), // output wire [7 : 0] probe_out8 68 .probe_out9(add2), // output wire [7 : 0] probe_out9 69 .probe_out10(data1), // output wire [7 : 0] probe_out10 70 .probe_out11(data2), // output wire [7 : 0] probe_out11 71 .probe_out12(data3), // output wire [7 : 0] probe_out12 72 .probe_out13(finish_core_init), // output wire [0 : 0] probe_out13 73 .probe_out14(start_core_write), // output wire [0 : 0] probe_out14 74 .probe_out15(wait_core_int), // output wire [0 : 0] probe_out15 75 .probe_out16(finish_core_write) // output wire [0 : 0] probe_out16 76 ); 77 78 79 //-------------------------------------------------------------- 80 ila_0 U4 ( 81 .clk(clk_100M), // input wire clk 82 .probe0(start_write_rise), // input wire [0:0] probe0 83 .probe1(start_read_rise), // input wire [0:0] probe1 84 .probe2(m_axi_awvalid), // input wire [0:0] probe2 85 .probe3(m_axi_wvalid), // input wire [0:0] probe3 86 .probe4(m_axi_arvalid), // input wire [0:0] probe4 87 .probe5(m_axi_rready), // input wire [0:0] probe5 88 .probe6(m_axi_bready), // input wire [0:0] probe6 89 .probe7(s_axi_awready), // input wire [0:0] probe7 90 .probe8(s_axi_arready), // input wire [0:0] probe8 91 .probe9(s_axi_wready), // input wire [0:0] probe9 92 .probe10(s_axi_rvalid), // input wire [0:0] probe10 93 .probe11(s_axi_bvalid), // input wire [0:0] probe11 94 .probe12(io0_i), // input wire [0:0] probe12 95 .probe13(io0_o), // input wire [0:0] probe13 96 .probe14(io0_t), // input wire [0:0] probe14 97 .probe15(io1_i), // input wire [0:0] probe15 98 .probe16(io1_o), // input wire [0:0] probe16 99 .probe17(io1_t), // input wire [0:0] probe17 100 .probe18(io2_i), // input wire [0:0] probe18 101 .probe19(io2_o), // input wire [0:0] probe19 102 .probe20(io2_t), // input wire [0:0] probe20 103 .probe21(io3_i), // input wire [0:0] probe21 104 .probe22(io3_o), // input wire [0:0] probe22 105 .probe23(io3_t), // input wire [0:0] probe23 106 .probe24(ss_i), // input wire [0:0] probe24 107 .probe25(ss_o), // input wire [0:0] probe25 108 .probe26(ss_t), // input wire [0:0] probe26 109 .probe27(m_axi_awaddr), // input wire [6:0] probe27 110 .probe28(m_axi_araddr), // input wire [6:0] probe28 111 .probe29(current_state), // input wire [6:0] probe29 112 .probe30(core_init_cnt), // input wire [6:0] probe30 113 .probe31(m_axi_wdata), // input wire [31:0] probe31 114 .probe32(m_axi_rdata), // input wire [31:0] probe32 115 .probe33(s_axi_rdata), // input wire [31:0] probe33 116 .probe34(core_write_cnt), // input wire [6:0] probe34 117 .probe35(axi_awaddr), // input wire [6:0] probe35 118 .probe36(next_state), // input wire [6:0] probe36 119 .probe37(axi_wdata) // input wire [31:0] probe37 120 ); 121 122 123 //-------------------------------------------------------------- 124 reg start_write; 125 always @(posedge clk_100M or posedge rst) 126 begin 127 if(rst) 128 start_write <= 1'b0; 129 130 else if (current_state == 0 && core_init_en) 131 begin 132 if(core_init_cnt == 0) 133 begin 134 if(start_core_init_rise) 135 start_write <= 1'b1; 136 else 137 start_write <= 1'b0; 138 end 139 140 else if(core_init_cnt == 2) 141 begin 142 if(finish_core_init_rise) 143 start_write <= 1'b1; 144 else 145 start_write <= 1'b0; 146 end 147 148 else 149 start_write <= 1'b1; 150 end 151 152 else if(current_state == 0 && core_write_en) 153 begin 154 if(core_write_cnt == 0) 155 begin 156 if(start_core_write_rise) 157 start_write <= 1'b1; 158 else 159 start_write <= 1'b0; 160 end 161 162 else if(core_write_cnt == 19) 163 begin 164 if(wait_core_int_rise) 165 start_write <= 1'b1; 166 else 167 start_write <= 1'b0; 168 end 169 170 else if(core_write_cnt == 21) 171 if(finish_core_write_rise) 172 start_write <= 1'b1; 173 else 174 start_write <= 1'b0; 175 176 else 177 start_write <= 1'b1; 178 end 179 180 else 181 start_write <= 1'b0; 182 end 183 184 185 //-------------------------------------------------------------- 186 reg start_write_delay; 187 wire start_write_rise; 188 189 reg start_read_delay; 190 wire start_read_rise; 191 192 reg start_core_init_delay; 193 wire start_core_init_rise; 194 195 reg finish_core_init_delay; 196 wire finish_core_init_rise; 197 198 reg start_core_write_delay; 199 wire start_core_write_rise; 200 201 reg wait_core_int_delay; 202 wire wait_core_int_rise; 203 204 reg finish_core_write_delay; 205 wire finish_core_write_rise; 206 207 208 always @(posedge clk_100M or posedge rst) 209 begin 210 if (rst) 211 begin 212 start_write_delay <= 1'b0; 213 start_read_delay <= 1'b0; 214 start_core_init_delay <= 1'b0; 215 finish_core_init_delay <= 1'b0; 216 start_core_write_delay <= 1'b0; 217 wait_core_int_delay <= 1'b0; 218 finish_core_write_delay <= 1'b0; 219 220 end 221 else 222 begin 223 start_write_delay <= start_write; 224 start_read_delay <= start_read; 225 start_core_init_delay <= start_core_init; 226 finish_core_init_delay <= finish_core_init; 227 start_core_write_delay <= start_core_write; 228 wait_core_int_delay <= wait_core_int; 229 finish_core_write_delay <= finish_core_write; 230 231 end 232 end 233 234 assign start_write_rise = !start_write_delay && start_write; 235 assign start_read_rise = !start_read_delay && start_read; 236 assign start_core_init_rise = !start_core_init_delay && start_core_init; 237 assign finish_core_init_rise = !finish_core_init_delay && finish_core_init; 238 assign start_core_write_rise = !start_core_write_delay && start_core_write; 239 assign wait_core_int_rise = !wait_core_int_delay && wait_core_int; 240 assign finish_core_write_rise = !finish_core_write_delay && finish_core_write; 241 242 //-------------------------------------------------------------- 243 244 parameter DUMMY_DATA = 8'hFF; 245 reg [6:0]axi_awaddr; 246 reg [31:0]axi_wdata; 247 248 reg [6:0]core_init_cnt; 249 reg [6:0]core_write_cnt; 250 always @(posedge clk_100M or posedge rst) 251 begin 252 if (rst) 253 begin 254 core_init_cnt <= 0; 255 core_write_cnt <= 0; 256 end 257 else if (current_state == 0 && core_init_en) 258 begin 259 case(core_init_cnt) 260 261 0: 262 begin 263 axi_awaddr <= 7'h40; 264 axi_wdata <= 32'h0000000A; 265 end 266 267 1: 268 begin 269 axi_awaddr <= 7'h1C; 270 axi_wdata <= 32'h80000000; 271 end 272 273 2: 274 begin 275 axi_awaddr <= 7'h28; 276 axi_wdata <= 32'h00000004; 277 end 278 279 default: 280 begin 281 axi_awaddr <= 7'h00; 282 axi_wdata <= 32'h00000000; 283 end 284 285 endcase 286 287 end 288 289 else if(current_state == 3 && core_init_en) 290 begin 291 if(core_init_cnt < 2) 292 core_init_cnt <= core_init_cnt + 1'b1; 293 else 294 core_init_cnt <= 0; 295 end 296 297 else if(current_state == 0 && core_write_en) 298 begin 299 case(core_write_cnt) 300 /* 301 0: 302 begin 303 axi_awaddr <= 7'h70; 304 axi_wdata <= 32'hFFFFFFFF; 305 end 306 */ 307 0: 308 begin 309 axi_awaddr <= 7'h60; 310 axi_wdata <= 32'h000001E6; 311 end 312 313 1: 314 begin 315 axi_awaddr <= 7'h60; 316 axi_wdata <= 32'h00000186; 317 end 318 319 2: 320 begin 321 axi_awaddr <= 7'h68; 322 axi_wdata <= {24'h000000,cmd}; 323 end 324 325 3: 326 begin 327 axi_awaddr <= 7'h68; 328 axi_wdata <= {24'h000000,add0}; 329 end 330 331 4: 332 begin 333 axi_awaddr <= 7'h68; 334 axi_wdata <= {24'h000000,add1}; 335 end 336 337 5: 338 begin 339 axi_awaddr <= 7'h68; 340 axi_wdata <= {24'h000000,add2}; 341 end 342 343 6: 344 begin 345 axi_awaddr <= 7'h68; 346 axi_wdata <= {24'h000000,data1}; 347 end 348 349 7: 350 begin 351 axi_awaddr <= 7'h68; 352 axi_wdata <= {24'h000000,data2}; 353 end 354 355 8: 356 begin 357 axi_awaddr <= 7'h68; 358 axi_wdata <= {24'h000000,data3}; 359 end 360 361 9: 362 begin 363 axi_awaddr <= 7'h68; 364 axi_wdata <= {24'h000000,DUMMY_DATA}; 365 end 366 367 10: 368 begin 369 axi_awaddr <= 7'h68; 370 axi_wdata <= {24'h000000,DUMMY_DATA}; 371 end 372 373 11: 374 begin 375 axi_awaddr <= 7'h68; 376 axi_wdata <= {24'h000000,DUMMY_DATA}; 377 end 378 379 12: 380 begin 381 axi_awaddr <= 7'h68; 382 axi_wdata <= {24'h000000,DUMMY_DATA}; 383 end 384 385 13: 386 begin 387 axi_awaddr <= 7'h68; 388 axi_wdata <= {24'h000000,DUMMY_DATA}; 389 end 390 391 14: 392 begin 393 axi_awaddr <= 7'h68; 394 axi_wdata <= {24'h000000,DUMMY_DATA}; 395 end 396 397 15: 398 begin 399 axi_awaddr <= 7'h68; 400 axi_wdata <= {24'h000000,DUMMY_DATA}; 401 end 402 403 16: 404 begin 405 axi_awaddr <= 7'h68; 406 axi_wdata <= {24'h000000,DUMMY_DATA}; 407 end 408 409 17: 410 begin 411 axi_awaddr <= 7'h70; 412 axi_wdata <= 32'h00000000; 413 end 414 415 18: 416 begin 417 axi_awaddr <= 7'h60; 418 axi_wdata <= 32'h00000086; 419 end 420 421 19: 422 begin 423 axi_awaddr <= 7'h20; 424 axi_wdata <= 32'h00000004; 425 end 426 427 20: 428 begin 429 axi_awaddr <= 7'h70; 430 axi_wdata <= 32'hFFFFFFFF; 431 end 432 433 21: 434 begin 435 axi_awaddr <= 7'h60; 436 axi_wdata <= 32'h00000186; 437 end 438 439 default: 440 begin 441 axi_awaddr <= 7'h00; 442 axi_wdata <= 32'h00000000; 443 end 444 445 endcase 446 end 447 448 else if(current_state == 3 && core_write_en) 449 begin 450 if(core_write_cnt < 21) 451 core_write_cnt <= core_write_cnt + 1'b1; 452 else 453 core_write_cnt <= 0; 454 end 455 456 end 457 458 //-------------------------------------------------------------- 459 reg [6:0]current_state; 460 reg [6:0]next_state; 461 always @ (posedge clk_100M or posedge rst) 462 begin 463 if(rst) 464 current_state <= IDLE; 465 else 466 current_state <= next_state; 467 end 468 469 //-------------------------------------------------------------- 470 parameter [4:0] IDLE = 5'd0 , 471 WRITE_START = 5'd1 , 472 WRITE_VALID = 5'd2 , 473 WRITE_READY = 5'd3 , 474 WRITE_BREADY = 5'd4 , 475 WRITE_END = 5'd5 , 476 READ_START = 5'd11 , 477 READ_VALID = 5'd12 , 478 READ_READY = 5'd13 , 479 READ_FINISH = 5'd14 , 480 READ_END = 5'd15 ; 481 482 always @ (*) 483 begin 484 next_state = IDLE; 485 case(current_state) 486 IDLE: 487 begin 488 if(start_write_rise) 489 next_state = WRITE_START; 490 else if(start_read_rise) 491 next_state = READ_START; 492 else 493 next_state = IDLE; 494 end 495 496 WRITE_START: 497 begin 498 next_state = WRITE_VALID; 499 end 500 501 WRITE_VALID: 502 begin 503 if(s_axi_awready && s_axi_wready) 504 next_state = WRITE_READY; 505 else 506 next_state = WRITE_VALID; 507 end 508 509 WRITE_READY: 510 begin 511 if(s_axi_bvalid) 512 next_state = WRITE_BREADY; 513 else 514 next_state = WRITE_READY; 515 end 516 517 WRITE_BREADY: 518 begin 519 next_state = WRITE_END; 520 end 521 522 WRITE_END: 523 begin 524 next_state = IDLE; 525 end 526 527 READ_START: 528 begin 529 next_state = READ_VALID; 530 end 531 532 READ_VALID: 533 begin 534 if(s_axi_arready) 535 next_state = READ_READY; 536 else 537 next_state = READ_VALID; 538 end 539 540 READ_READY: 541 begin 542 if(s_axi_rvalid) 543 next_state = READ_FINISH; 544 else 545 next_state = READ_READY; 546 end 547 548 READ_FINISH: 549 begin 550 next_state = READ_END; 551 end 552 553 READ_END: 554 begin 555 next_state = IDLE; 556 end 557 558 endcase 559 end 560 561 //------------------------------------------------------------- 562 reg m_axi_awvalid; 563 reg m_axi_wvalid; 564 reg m_axi_arvalid; 565 566 reg m_axi_rready; 567 reg m_axi_bready; 568 569 reg [6:0]m_axi_awaddr; 570 reg [6:0]m_axi_araddr; 571 572 reg [31:0]m_axi_wdata; 573 reg [31:0]m_axi_rdata; 574 575 576 always @(posedge clk_100M or posedge rst) 577 begin 578 if (rst) 579 begin 580 m_axi_awvalid <= 1'b0; 581 m_axi_wvalid <= 1'b0; 582 m_axi_arvalid <= 1'b0; 583 m_axi_rready <= 1'b0; 584 m_axi_bready <= 1'b0; 585 m_axi_awaddr <= 0; 586 m_axi_araddr <= 0; 587 m_axi_wdata <= 0; 588 m_axi_rdata <= 0; 589 end 590 else 591 begin 592 593 m_axi_awvalid <= 1'b0; 594 m_axi_wvalid <= 1'b0; 595 m_axi_arvalid <= 1'b0; 596 m_axi_rready <= 1'b0; 597 m_axi_bready <= 1'b0; 598 599 case(current_state) 600 //IDLE: 601 602 WRITE_START: 603 begin 604 m_axi_awaddr <= axi_awaddr; 605 m_axi_wdata <= axi_wdata; 606 m_axi_awvalid <= 1'b1; 607 m_axi_wvalid <= 1'b1; 608 m_axi_bready <= 1'b1; 609 end 610 611 WRITE_VALID: 612 begin 613 m_axi_awvalid <= 1'b1; 614 m_axi_wvalid <= 1'b1; 615 m_axi_bready <= 1'b1; 616 end 617 618 WRITE_READY: 619 begin 620 m_axi_bready <= 1'b1; 621 end 622 623 //WRITE_BREADY: 624 //WRITE_END: 625 626 READ_START: 627 begin 628 m_axi_araddr <= axi_araddr; 629 m_axi_arvalid <= 1'b1; 630 end 631 632 READ_VALID: 633 begin 634 m_axi_arvalid <= 1'b1; 635 end 636 637 //READ_READY: 638 639 READ_FINISH: 640 begin 641 m_axi_rdata <= s_axi_rdata; 642 m_axi_rready <= 1'b1; 643 end 644 645 //READ_END: 646 647 default: 648 begin 649 m_axi_awvalid <= 1'b0; 650 m_axi_wvalid <= 1'b0; 651 m_axi_arvalid <= 1'b0; 652 m_axi_rready <= 1'b0; 653 m_axi_bready <= 1'b0; 654 end 655 656 endcase 657 658 end 659 end 660 661 //------------------------------------------------------------- 662 wire s_axi_awready; 663 wire s_axi_arready; 664 wire s_axi_wready; 665 wire s_axi_rvalid; 666 wire s_axi_bvalid; 667 wire [31:0]s_axi_rdata; 668 669 wire io0_i; 670 wire io0_o; 671 wire io0_t; 672 wire io1_i; 673 wire io1_o; 674 wire io1_t; 675 wire io2_i; 676 wire io2_o; 677 wire io2_t; 678 wire io3_i; 679 wire io3_o; 680 wire io3_t; 681 wire ss_i; 682 wire ss_o; 683 wire ss_t; 684 685 axi_quad_spi_0 U1 ( 686 .ext_spi_clk(clk_100M), // input wire ext_spi_clk 687 .s_axi_aclk(clk_100M), // input wire s_axi_aclk 688 .s_axi_aresetn(~rst), // input wire s_axi_aresetn 689 .s_axi_awaddr(m_axi_awaddr), // input wire [6 : 0] s_axi_awaddr 690 .s_axi_awvalid(m_axi_awvalid), // input wire s_axi_awvalid 691 .s_axi_awready(s_axi_awready), // output wire s_axi_awready 692 .s_axi_wdata(m_axi_wdata), // input wire [31 : 0] s_axi_wdata 693 .s_axi_wstrb(4'b1111), // input wire [3 : 0] s_axi_wstrb 694 .s_axi_wvalid(m_axi_wvalid), // input wire s_axi_wvalid 695 .s_axi_wready(s_axi_wready), // output wire s_axi_wready 696 .s_axi_bresp(), // output wire [1 : 0] s_axi_bresp 697 .s_axi_bvalid(s_axi_bvalid), // output wire s_axi_bvalid 698 .s_axi_bready(m_axi_bready), // input wire s_axi_bready 699 .s_axi_araddr(m_axi_araddr), // input wire [6 : 0] s_axi_araddr 700 .s_axi_arvalid(m_axi_arvalid), // input wire s_axi_arvalid 701 .s_axi_arready(s_axi_arready), // output wire s_axi_arready 702 .s_axi_rdata(s_axi_rdata), // output wire [31 : 0] s_axi_rdata 703 .s_axi_rresp(), // output wire [1 : 0] s_axi_rresp 704 .s_axi_rvalid(s_axi_rvalid), // output wire s_axi_rvalid 705 .s_axi_rready(m_axi_rready), // input wire s_axi_rready 706 .io0_i(io0_i), // input wire io0_i 707 .io0_o(io0_o), // output wire io0_o 708 .io0_t(io0_t), // output wire io0_t 709 .io1_i(io1_i), // input wire io1_i 710 .io1_o(io1_o), // output wire io1_o 711 .io1_t(io1_t), // output wire io1_t 712 .io2_i(io2_i), // input wire io2_i 713 .io2_o(io2_o), // output wire io2_o 714 .io2_t(io2_t), // output wire io2_t 715 .io3_i(io3_i), // input wire io3_i 716 .io3_o(io3_o), // output wire io3_o 717 .io3_t(io3_t), // output wire io3_t 718 .ss_i(ss_i), // input wire [0 : 0] ss_i 719 .ss_o(ss_o), // output wire [0 : 0] ss_o 720 .ss_t(ss_t), // output wire ss_t 721 .cfgclk(cfgclk), // output wire cfgclk 722 .cfgmclk(cfgmclk), // output wire cfgmclk 723 .eos(eos), // output wire eos 724 .preq(preq), // output wire preq 725 .ip2intc_irpt(ip2intc_irpt) // output wire ip2intc_irpt 726 ); 727 728 IOBUF dq0( 729 .IO (spi_dq[0]), 730 .O (io0_i), 731 .I (io0_o), 732 .T (io0_t) 733 ); 734 735 IOBUF dq1( 736 .IO (spi_dq[1]), 737 .O (io1_i), 738 .I (io1_o), 739 .T (io1_t) 740 ); 741 742 IOBUF dq2( 743 .IO (spi_dq[2]), 744 .O (io2_i), 745 .I (io2_o), 746 .T (io2_t) 747 ); 748 749 IOBUF dq3( 750 .IO (spi_dq[3]), 751 .O (io3_i), 752 .I (io3_o), 753 .T (io3_t) 754 ); 755 756 IOBUF spiss( 757 .IO (spi_ss), 758 .O (ss_i), 759 .I (ss_o), 760 .T (ss_t) 761 ); 762 763 endmodule
