信号滤波模块verilog代码
1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: chensimin 5 // 6 // Create Date: 2017/12/14 17:15:25 7 // Design Name: 8 // Module Name: glitch_filter_1 9 // Project Name: 10 // Target Devices: 11 // Tool Versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 module glitch_filter_1 #( 22 parameter WIDTH = 32, 23 parameter CNT_CLK_FREQUENCY = 25) // frequency cnt_clk in MHz 24 ( 25 input wire cnt_clk, 26 input wire [WIDTH-1:0] delay_time_high, 27 input wire [WIDTH-1:0] delay_time_low, 28 input wire clk, 29 input wire rst, 30 input wire sign_src, 31 output wire sign_src_filter 32 ); 33 34 localparam UNLOCK = 1'b0; 35 localparam LOCK = 1'b1; 36 37 reg get_time_1us; 38 reg [WIDTH-1:0]m; 39 always @ ( posedge cnt_clk or posedge rst ) 40 begin 41 if( rst ) 42 begin 43 get_time_1us <= 1'b0; 44 m <= 0; 45 end 46 else if( m == CNT_CLK_FREQUENCY - 1 ) 47 begin 48 get_time_1us <= 1'b1; 49 m <= 0; 50 end 51 else 52 begin 53 get_time_1us <= 1'b0; 54 m <= m + 1'b1; 55 end 56 end 57 58 reg [WIDTH-1:0]i; 59 reg [WIDTH-1:0]k; 60 reg get_delay_time_high; 61 reg get_delay_time_low; 62 reg current_state; 63 reg next_state; 64 always @ ( posedge cnt_clk or posedge rst ) 65 begin 66 if( rst ) 67 begin 68 get_delay_time_high <= 1'b0; 69 get_delay_time_low <= 1'b0; 70 i <= 0; 71 k <= 0; 72 end 73 else 74 begin 75 get_delay_time_high <= 1'b0; 76 get_delay_time_low <= 1'b0; 77 case( current_state ) 78 UNLOCK: 79 if( sign_src == 1'b1 ) 80 begin 81 if( i == delay_time_high - 1 ) 82 begin 83 get_delay_time_high <= 1'b1; 84 i <= 0; 85 end 86 else if( get_time_1us ) 87 begin 88 i <= i + 1'b1; 89 end 90 end 91 else 92 begin 93 i <= 0; 94 end 95 LOCK: 96 if( sign_src == 1'b0 ) 97 begin 98 if( k == delay_time_low - 1 ) 99 begin 100 get_delay_time_low <= 1'b1; 101 k <= 0; 102 end 103 else if( get_time_1us ) 104 begin 105 k <= k + 1'b1; 106 end 107 end 108 else 109 begin 110 k <= 0; 111 end 112 endcase 113 end 114 end 115 116 always @ ( posedge cnt_clk or posedge rst ) 117 begin 118 if( rst ) 119 current_state <= UNLOCK; 120 else 121 current_state <= next_state; 122 end 123 124 always @ ( * ) 125 begin 126 case( current_state ) 127 UNLOCK: 128 if( get_delay_time_high == 1'b1 ) 129 next_state = LOCK; 130 else 131 next_state = UNLOCK; 132 LOCK: 133 if( get_delay_time_low == 1'b1) 134 next_state = UNLOCK; 135 else 136 next_state = LOCK; 137 endcase 138 end 139 140 reg sign_src_r; 141 always @ ( posedge cnt_clk or posedge rst ) 142 begin 143 if( rst ) 144 sign_src_r <= 1'b0; 145 else 146 begin 147 case( current_state ) 148 UNLOCK: 149 sign_src_r <= 1'b0; 150 LOCK: 151 sign_src_r <= 1'b1; 152 endcase 153 end 154 end 155 156 reg [1:0]sign_src_r_delay; 157 always @ ( posedge clk or posedge rst ) 158 if(rst) 159 sign_src_r_delay <= 2'b00; 160 else 161 sign_src_r_delay <= {sign_src_r_delay[0], sign_src_r}; 162 163 assign sign_src_filter = sign_src_r_delay[1]; 164 165 endmodule 166 167 168 169 /* 170 add_force {/glitch_filter_1/cnt_clk} -radix hex {0 0ns} {1 50000ps} -repeat_every 100000ps 171 add_force {/glitch_filter_1/rst} -radix hex {1 0ns} {0 100000ps} 172 add_force {/glitch_filter_1/sign_src} -radix hex {0 0ns} {1 198000ps} {0 232000ps} {1 308000ps} {0 354000ps} {1 400000ps} {0 450000ps} {1 552000ps} {0 2550000ps} {1 2740000ps} {0 2850000ps} {1 2950000ps} {0 3550000ps} 173 add_force {/glitch_filter_1/delay_time_high} -radix hex {4 0ns} 174 add_force {/glitch_filter_1/delay_time_low} -radix hex {5 0ns} 175 add_force {/glitch_filter_1/clk} -radix hex {0 0ns} {1 25000ps} -repeat_every 50000ps 176 177 178 179 */
备注：对易产生锯齿的信号进行滤波，增强其稳定性。
