verilog编码规范

verilog编码规范

1.Register with Rising-Edge Coding Example (Verilog)

　　Flip-Flops and Registers Control Signals
　　Flip-Flops and Registers control signals include:
　　• Clocks
　　• Asynchronous and synchronous set and reset signals
　　• Clock enable

Filename: registers_1.v
// 8-bit Register with
// Rising-edge Clock
// Active-high Synchronous Clear
// Active-high Clock Enable
// File: registers_1.v
module registers_1(d_in,ce,clk,clr,dout);
input [7:0] d_in;
input ce;
input clk;
input clr;
output [7:0] dout;
reg [7:0] d_reg;
always @ (posedge clk)
begin
　　if(clr)
　　　　d_reg <= 8'b0;
　　else if(ce)
　　　　d_reg <= d_in;
end
assign dout = d_reg;
endmodule

2.Latch With Positive Gate and Asynchronous Reset Coding Example (Verilog)

Filename: latches.v
// Latch with Positive Gate and Asynchronous Reset
// File: latches.v
module latches (
　　input G,
　　input D,
　　input CLR,
　　output reg Q
);
always @ *
begin
　　if(CLR)
　　　　Q = 0;
　　else if(G)
　　　　Q = D;
end
endmodule

 3.Tristate Description Using Concurrent Assignment Coding Example (Verilog)

Filename: tristates_2.v
// Tristate Description Using Concurrent Assignment
// File: tristates_2.v
//
module tristates_2 (T, I, O);
input T, I;
output O;
assign O = (~T) ? I: 1'bZ;
endmodule

4.Tristate Description Using Combinatorial Always Block Coding Example(Verilog)

Filename: tristates_1.v
// Tristate Description Using Combinatorial Always Block
// File: tristates_1.v
//
module tristates_1 (T, I, O);
input T, I;
output O;
reg O;
always @(T or I)
begin
　　if (~T)
　　　　O = I;
　　else
　　　　O = 1'bZ;
end
endmodule

5.Shift Register Coding Example One (Verilog)

　　Static Shift Register Elements
　　A static Shift Register usually involves:
　　• A clock
　　• An optional clock enable
　　• A serial data input
　　• A serial data output

Filename: shift_registers_0.v
// 8-bit Shift Register
// Rising edge clock
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk)
begin
    if (clken)
        shreg = {shreg[WIDTH-2:0], SI};
end

assign SO = shreg[WIDTH-1];

endmodule